Datasheet

143
7593L–AVR–09/12
AT90USB64/128
15.10.17 TIMSK1 – Timer/Counter1 Interrupt Mask Register
15.10.18 TIMSK3 – Timer/Counter3 Interrupt Mask Register
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 68) is executed when the ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed w hen the OCFnC Flag, located in
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed when the OCFnB Flag, located in
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed when the OCFnA Flag, located in
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(see “Interrupts” on page 68) is executed when the TOVn Flag, located in TIFRn, is set.
15.10.19 TIFR1 – Timer/Counter1 Interrupt Flag Register
15.10.20 TIFR3 – Timer/Counter3 Interrupt Flag Register
Bit 765432 10
– –ICIE1– OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 765432 10
– –ICIE3– OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
– –ICF1– OCF1C OCF1B OCF1A TOV1 TIFR1
Read/write R R R/W R R/W R/W R/W R/W
Initial value00000000
Bit 76543210
– –ICF3– OCF3C OCF3B OCF3A TOV3 TIFR3
Read/write R R R/W R R/W R/W R/W R/W
Initial value00000000