Features • High performance, low power AVR® 8-bit Microcontroller • Advanced RISC architecture • • • • • • – 135 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 16MIPS throughput at 16MHz – On-chip 2-cycle multiplier Non-volatile program and data memories – 64/128Kbytes of in-system self-programmable flash • Endurance: 100,000 write/erase cycles – Optional Boot Code section with independent lock bits • USB boot load
• • • • • 2 – Real time counter with separate oscillator – Four 8-bit PWM channels – Six PWM channels with programmable resolution from 2 to 16 bits – Output compare modulator – 8-channels, 10-bit ADC – Programmable serial USART – Master/slave SPI serial interface – Byte oriented 2-wire serial interface – Programmable watchdog timer with separate on-chip oscillator – On-chip analog comparator – Interrupt and wake-up on pin change Special microcontroller features – Power-on reset and programmable brown-o
AT90USB64/128 1. Pin configurations AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout Atmel AT90USB64/128-TQFP. 64 Figure 1-1. (INT.6/AIN.0) PE6 1 48 PA3 (AD3) (INT.7/AIN.
AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout Atmel AT90USB64/128-QFN. 64 Figure 1-2. (INT.6/AIN.0) PE6 1 48 PA3 (AD3) (INT.7/AIN.1/UVcon) PE7 2 47 PA4 (AD4) 46 PA5 (AD5) 45 PA6 (AD6) UVcc 3 D- 4 D+ 5 44 PA7 (AD7) UGnd 6 43 PE2 (ALE/HWB) UCap 7 42 PC7 (A15/IC.
AT90USB64/128 2. Overview The Atmel® AVR® AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the Atmel® AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90USB64/128 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Block diagram PF7 - PF0 VCC PC7 - PC0 PA7 - P A0 POR TA DRIVERS POR TF DRIVERS RESET Block diagram. XT AL2 Figure 2-1. XT AL1 2.1 POR TC DRIVERS GND DATA DIR. REG. PORT F DATA REGISTER PORT F DATA DIR. REG. PORT A DATA REGISTER PORT A DATA REGISTER PORT C DATA DIR. REG. PORT C 8-BIT DA TA BUS POR - BOD RESET AVCC INTERNAL OSCILLA TOR CALIB.
AT90USB64/128 architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
2.2 2.2.1 Pin descriptions VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 AVCC Analog supply voltage. 2.2.4 Port A (PA7..PA0) Port A is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
AT90USB64/128 2.2.8 Port E (PE7..PE0) Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.
2.2.18 XTAL2 Output from the inverting oscillator amplifier. 2.2.19 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.2.20 AREF This is the analog reference pin for the A/D Converter. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.
AT90USB64/128 5. AVR CPU core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural overview Figure 5-1. Block diagram of the AVR architecture.
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
AT90USB64/128 5.4 Status register The status register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
• Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction set summary” on page 423 for detailed information. 5.5 General purpose register file The register file is optimized for the AVR Enhanced RISC instruction set.
AT90USB64/128 Figure 5-3. The X-, Y-, and Z-registers. 15 XH XL 7 X-register 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.
5.6.1 RAMPZ - Extended Z-pointer register for ELPM/SPM Bit 7 6 5 4 3 2 1 0 RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 5-4. Note that LPM is not affected by the RAMPZ setting. Figure 5-4. Bit (individually) The Z-pointer used by ELPM and SPM.
AT90USB64/128 Figure 5-6. Single cycle ALU operation. T1 T2 T3 T4 clkCPU Total execution time Register operands fetch ALU operation execute Result write back 5.8 Reset and interrupt handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
AT90USB64/128 Assembly code example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C code example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 5.8.1 Interrupt response time The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum.
6. Atmel AVR AT90USB64/128 memories This section describes the different memories in the AT90USB64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90USB64/128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. Table 6-1. Memory mapping.
AT90USB64/128 software protection are described in detail in “Memory programming” on page 359. “Memory programming” on page 359 contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface. Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description and ELPM - Extended Load Program Memory instruction description).
An optional external data SRAM can be used with the Atmel AT90USB64/128. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest 4,352/8,448 bytes, so when using 64KB (65,536 bytes) of External Memory, 61,184/57,088 Bytes of External Memory are available.
AT90USB64/128 Figure 6-2. Data memory map. Data memory 32 registers 64 I/O registers 160 Ext I/O reg. $0000 - $001F $0020 - $005F $0060 - $00FF ISRAM start Internal SRAM (8192 x 8) ISRAM end XMem start External SRAM (0 - 64K x 8) $FFFF 6.2.1 Data memory access times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 6-3.
Figure 6-3. On-chip data SRAM access cycles. T1 T2 T3 clkCPU Address Compute address Address valid Write Data WR Read Data RD Memory access instruction 6.3 Next instruction EEPROM data memory The Atmel AT90USB64/128 contains 2K/4K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
AT90USB64/128 6.3.2 EEARH and EEARL – The EEPROM Address Register Bit Read/write Initial value 15 14 13 12 11 10 9 8 – – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 X X X X X X X X X X X X • Bits 15..12 – Res: Reserved bits These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
Table 6-2. EEPROM Mode bits. EEPM1 EEPM0 Programming time 0 0 3.4ms Erase and Write in one operation (atomic operation) 0 1 1.8ms Erase only 1 0 1.8ms Write only 1 1 – Operation Reserved for future use • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.
AT90USB64/128 When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.
Assembly code example (1) EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C code example (1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
AT90USB64/128 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
6.4 I/O memory The I/O space definition of the Atmel AT90USB64/128 is shown in “Register summary” on page 419. All AT90USB64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
AT90USB64/128 6.5 External memory interface With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCDdisplay, A/D, and D/A. The main features are: • • • • 6.5.
When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section “I/O-ports” on page 71. The XMEM interface will auto-detect whether an access is internal or external.
AT90USB64/128 6.5.4 Pull-up and bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be disabled and enabled in software as described in “XMCRB – External Memory Control Register B” on page 36.
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external). External data memory cycles with SRWn1 = 0 and SRWn0 = 1 (1). Figure 6-7. T1 T2 T3 T4 T5 System clock (CLK CPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev.
AT90USB64/128 External data memory cycles with SRWn1 = 1 and SRWn0 = 1 (1). Figure 6-9. T1 T2 T3 T4 T5 T6 T7 System clock (CLK CPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data XX Write Address Data WR Address Read Data Data RD Note: 6.5.6 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
Table 6-4. Sector limits with different settings of SRL2..0.
AT90USB64/128 stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is one. • Bit 6..3 – Res: Reserved Bits These bits are reserved and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices. • Bit 2..
Figure 6-10. Address map with 32KB external memory. Memory configuration A AVR memory map 0x0000 External 32K SRAM 0x0000 Internal memory 0x20FF 0x2100 0x7FFF 0x8000 ISRAM end XMem start External 0x7FFF memory ISRAM end + 0x8000 XMem start + 0x8000 (Unused) 0xFFFF 6.5.
AT90USB64/128 Assembly code example (1) ; ; ; ; ; OFFSET is defined to 0x4000 to ensure external memory access Configure Port C (address high byte) to output 0x00 when the pins are released for normal Port Pin operation ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16 ; release PC7:6 ldi r16, (1<
7. System clock and clock options 7.1 Clock systems and their distribution Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power management and sleep modes” on page 51. The clock systems are detailed below. Figure 7-1. Clock distribution.
AT90USB64/128 7.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 7.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
dependent as shown in “Atmel AT90USB64/128 typical characteristics” on page 404. Table 7-2. Number of watchdog oscillator cycles. Typical time-out (VCC = 5.0V) Typical time-out (VCC = 3.0V) Number of cycles 0ms 0ms 0 4.1ms 4.3ms 512 65ms 69ms 8K (8,192) Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not monitor the actual voltage and it will be required to select a delay longer than the VCC rise time.
AT90USB64/128 Figure 7-2. Crystal oscillator connections. C2 XTAL2 C1 XTAL1 GND The low power oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-3. Table 7-3. Notes: Low power crystal oscillator operating modes (3). Frequency range (1) [MHz] CKSEL3..1 Recommended range for capacitors C1 and C2 [pF] 0.4 - 0.9 100 (2) – 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 8.
Table 7-4. Start-up times for the low power crystal oscillator clock selection. (Continued) Start-up time from power-down and power-save Additional delay from reset (VCC = 5.0V) CKSEL0 SUT1..0 Crystal Oscillator, BOD enabled 16KCK 14CK 1 01 Crystal Oscillator, fast rising power 16KCK 14CK + 4.1ms 1 10 Crystal Oscillator, slowly rising power 16KCK 14CK + 65ms 1 11 Oscillator source / power conditions Notes: 1.
AT90USB64/128 Note: 7.5 1. These options should only be used if frequency stability at start-up is not important for the application. Calibrated internal RC oscillator The calibrated internal RC oscillator by default provides a 8.0MHz clock. The frequency is nominal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See “System clock prescaler” on page 47 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 7-7.
be calibrated to any frequency in the range 7.3 - 8.1MHz within ±10% accuracy. Calibration outside that range is not guaranteed. Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or Flash write may fail. The CAL7 bit determines the range of operation for the oscillator.
AT90USB64/128 Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System clock prescaler” on page 47 for details. 7.7 Clock output buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system.
7.9.1 CLKPR – Clock Prescale Register Bit 7 6 5 4 3 2 1 CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 0 CLKPS0 Read/write R/W R R R R/W R/W R/W R/W Initial value 0 0 0 0 See bit description CLKPR • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
AT90USB64/128 7.10 CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock division factor 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved PLL The PLL is used to generate internal high frequency (48MHz) clock for USB interface, the PLL input is generated from an external low-frequency (the crystal oscillator or external clock input pin from XTAL1). The internal RC oscillator can not be used for USB operations. 7.10.
Table 7-11. PLL input prescaler configurations. PLLP2 PLLP1 PLLP0 Clock division factor External XTAL required for USB operation [MHz] 0 0 0 Reserved - 0 0 1 Reserved - 0 1 0 Reserved - 0 1 1 4 8 1 0 0 Reserved - Note: (1) 16 (1) 1 0 1 8 1 1 0 8 (2) 16 (2) 1 1 1 Reserved - 1. For Atmel AT90USB128x only. Do not use with Atmel AT90USB64x. 2. For AT90USB64x only. Do not use with AT90USB128x. • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started.
AT90USB64/128 8. Power management and sleep modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
8.1 Idle mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
AT90USB64/128 If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set. If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode. The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode.
8.7 Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
AT90USB64/128 8.7.2 PRR1 – Power Reduction Register 1 Bit 7 6 5 4 3 2 1 0 PRUSB – – – PRTIM3 – – PRUSART1 Read/write R/W R R R R/W R R R/W Initial value 0 0 0 0 0 0 0 0 PRR1 • Bit 7 - PRUSB: Power Reduction USB Writing a logic one to this bit shuts down the USB by stopping the clock to the module. When waking up the USB again, the USB should be re initialized to ensure proper operation. • Bit 6..4 - Res: Reserved bits These bits are reserved and will always read as zero.
8.8.3 Brown-out detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out detection” on page 60 for details on how to configure the Brown-out Detector. 8.8.
AT90USB64/128 9. System control and reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 9-1. Reset logic. DATA BUS PORF BORF EXTRF WDRF JTRF MCU status register (MCUSR) Power-on reset circuit Brown-out reset circuit BODLEVEL [2..0] Pull-up resistor SPIKE FILTER JTAG reset register Watchdog oscillator Clock generator Delay counters CK TIMEOUT CKSEL[3:0] SUT[1:0] Table 9-1. Reset characteristics. Symbol Parameter Condition Min. Power-on reset threshold voltage (rising) VPOT VPOR VCC start voltage to ensure internal poweron reset signal -0.
AT90USB64/128 voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. Figure 9-2. VCC MCU start-up, RESET tied to VCC. VPOR VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET Figure 9-3. VCC RESET TIMEOUT MCU start-up, RESET extended externally. VPOR VPOT VRST tTOUT INTERNAL RESET Note: 9.
Figure 9-4. External reset during operation. CC 9.5 Brown-out detection Atmel AT90USB64/128 has an on-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 9-2.
AT90USB64/128 Figure 9-5. Brown-out reset during operation. VCC VBOT+ VBOT- RESET tTOUT TIMEOUT INTERNAL RESET 9.6 Watchdog reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. Refer to page 63 for details on operation of the Watchdog Timer. Figure 9-6. Watchdog reset during operation. CC CK 9.6.
• Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
AT90USB64/128 9.8 Watchdog timer The Atmel AT90USB64/128 has an enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate on-chip oscillator • Three operating modes – Interrupt – System reset – Interrupt and system reset • Selectable time-out period from 16ms to 8s • Possible hardware fuse watchdog always on (WDTON) for fail-safe mode Watchdog timer. 128kHz OSCILLATOR WATCHDOG RESET WDE OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K Figure 9-7.
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watchdog Timer.
AT90USB64/128 Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use.
• Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
AT90USB64/128 . Table 9-6. Watchdog timer prescale select. WDP3 WDP2 WDP1 WDP0 Number of WDT oscillator cycles Typical time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16ms 0 0 0 1 4K (4096) cycles 32ms 0 0 1 0 8K (8192) cycles 64ms 0 0 1 1 16K (16384) cycles 0.125s 0 1 0 0 32K (32768) cycles 0.25s 0 1 0 1 64K (65536) cycles 0.5s 0 1 1 0 128K (131072) cycles 1.0s 0 1 1 1 256K (262144) cycles 2.0s 1 0 0 0 512K (524288) cycles 4.
10. Interrupts This section describes the specifics of the interrupt handling as performed in Atmel AT90USB64/128. For a general explanation of the AVR interrupt handling, refer to “Reset and interrupt handling” on page 17. 10.1 Interrupt vectors in AT90USB64/128 Table 10-1. 68 Reset and interrupt vectors. Vector no.
AT90USB64/128 Table 10-1. Reset and interrupt vectors. (Continued) Vector no.
Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to Section “Memory programming” on page 359 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
AT90USB64/128 11. I/O-ports 11.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
11.2 Ports as general digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 11-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 11-2. General digital I/O (1). PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 11.2.
AT90USB64/128 11.2.2 Toggling the pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 11.2.3 Switching between input and output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) occurs.
Figure 11-3. Synchronization when reading an externally applied pin value. SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
AT90USB64/128 Assembly code example (1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down.
AT90USB64/128 Table 11-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 11-5 on page 76 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 11-2. Generic description of overriding signals for alternate functions. Signal name Full name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
11.3.1 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE Read/write R/W R R R/W R R R/W R/W Initial value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the pin” on page 72 for more details about this feature. 11.3.
AT90USB64/128 Note: 1. ADA is short for ADdress Active and represents the time when address is output. See “External memory interface” on page 31 for details. Table 11-5. 11.3.3 Overriding signals for alternate functions in PA3..PA0.
OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function. PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source. • OC1B/PCINT6, bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B.
AT90USB64/128 PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source. • SS/PCINT0 – Port B, bit 0 SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
11.3.4 Alternate functions of Port C The Port C alternate function is as follows: Table 11-9. Port pin Port C pins alternate functions. Alternate function PC7 A15/IC.3/CLKO(External Memory interface address bit 15 or Input Capture Timer 3 or CLKO (Divided System Clock) PC6 A14/OC.3A(External Memory interface address bit 14 or Output Compare and PWM output A for Timer/Counter3) PC5 A13/OC.3B(External Memory interface address bit 13 or Output Compare and PWM output B for Timer/Counter3) PC4 A12/OC.
AT90USB64/128 Table 11-11. Overriding signals for alternate functions in PC3..PC0. 11.3.5 Signal name PC3/A11/T.
• ICP1 – Port D, bit 4 ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for Timer/Counter1. • INT3/TXD1 – Port D, bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. • INT2/RXD1 – Port D, bit 2 INT2, External Interrupt source 2.
AT90USB64/128 Table 11-13. Overriding signals for alternate functions PD7..PD4. Signal name PD7/T0 PD6/T1 PD5/XCK1 PD4/ICP1 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 XCK1 OUTPUT ENABLE 0 DDOV 0 0 1 0 PVOE 0 0 XCK1 OUTPUT ENABLE 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AIO – – – – Table 11-14. Overriding signals for alternate functions in PD3..PD0 (1).
11.3.6 Alternate functions of Port E The Port E pins with alternate functions are shown in Table 11-15. Table 11-15. Port E pins alternate functions. Port pin Alternate function PE7 INT7/AIN.1/UVCON (External Interrupt 7 Input, Analog Comparator Positive Input or VBUS Control) PE6 INT6/AIN.
AT90USB64/128 • ALE/HWB – Port E, bit 2 ALE is the external data memory Address latch enable. HWB allows to execute the boot loader section after reset when tied to ground during external reset pulse. The HWB mode of this pin is active only when the HWBE fuse is enable. • RD – Port E, bit 1 RD is the external data memory read control enable. • WR – Port E, bit 0 WR is the external data memory write control enable. Table 11-16. Overriding signals for alternate functions PE7..PE4. Signal name PE7/INT7/AIN.
11.3.7 Alternate functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 11-18. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. Table 11-18. Port F pins alternate functions.
AT90USB64/128 Table 11-19. Overriding signals for alternate functions in PF7..PF4. Signal name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV 1 0 1 1 DDOE JTAGEN JTAGEN JTAGEN JTAGEN DDOV 0 SHIFT_IR + SHIFT_DR 0 0 PVOE 0 JTAGEN 0 0 PVOV 0 TDO 0 0 DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV 0 0 0 0 DI – – – – AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCK/ADC4 INPUT Table 11-20.
11.4.2 DDRA – Port A Data Direction Register Bit 11.4.
AT90USB64/128 11.4.11 DDRD – Port D Data Direction Register Bit 11.4.12 7 6 5 4 3 2 1 0 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PIND – Port D Input Pins Address Bit 11.4.
12. External interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT7..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT7 ..0 are detected asynchronously.
AT90USB64/128 Table 12-1. ISCn1 ISCn0 0 0 The low level of INTn generates an interrupt request. 0 1 Any edge of INTn generates asynchronously an interrupt request. 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Note: Description 1. n = 3, 2, 1or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register.
• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether the external interrupt is activated on rising or falling edge or level sensed.
AT90USB64/128 12.0.7 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 PCMSK0 • Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..
13. Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1 or 3. 13.1 Internal clock source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
AT90USB64/128 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
14. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: • • • • • • • 14.
AT90USB64/128 The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See “Output compare unit” on page 100. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. 14.1.
Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
AT90USB64/128 Figure 14-3. Output Compare Unit, block diagram. DATA BUS OCRnx TCNTn = (8-bit comparator) OCFnx (int.req.) top bottom Waveform generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 14.
AT90USB64/128 the non-PWM modes refer to Table 14-1 on page 109. For fast PWM mode, refer to Table 14-2 on page 109, and for phase correct PWM refer to Table 14-3 on page 109. A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits. 14.
Figure 14-5. CTC mode, timing diagram. OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
AT90USB64/128 PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 14-6. Fast PWM mode, timing diagram.
feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 14.6.4 Phase correct PWM mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5.
AT90USB64/128 one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (see Table 14-3 on page 109). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 14-9. Timer/Counter timing diagram, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) MAX - 1 TCNTn MAX BOTTOM BOTTOM + 1 TOVn Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 14-10. Timer/Counter timing diagram, setting of OCF0x, with prescaler (fclk_I/O/8).
AT90USB64/128 • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting.
• Bits 5:4 – COM0B1:0: Compare Match Output B mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting.
AT90USB64/128 • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 14-7. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 103). Table 14-7.
strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved bits These bits are reserved bits and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “TCCR0A – Timer/Counter Control Register A” on page 108.
AT90USB64/128 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 14.8.
• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
AT90USB64/128 15. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • • • • • • • • • • • 15.
Figure 15-1. 16-bit Timer/Counter block diagram (1). Count Clear Direction TOVn (int.req.) Control logic TCLK Clock select Edge detector TOP Tn BOTTOM (From prescaler) Timer/Counter TCNTn = =0 OCFnA (Int.Req.) Waveform generation = OCnA OCRnA OCFnB (Int.Req.) Fixed TOP values Waveform generation DATABUS = OCnB OCRnB OCFnC (Int.Req.) Waveform generation = OCnC OCRnC ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge detector ICRn Noise canceler ICPn TCCRnA Note: 15.1.
AT90USB64/128 See “Output Compare units” on page 124.. The compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request.
Assembly code examples (1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C code examples (1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. See “About code examples” on page 10. The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
AT90USB64/128 The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
AT90USB64/128 15.4 Counter unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter unit block diagram. DATA BUS (8-bit) TOVn (Int.Req.
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 15.5 Input Capture unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit.
AT90USB64/128 Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location).
AT90USB64/128 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
15.7 Compare Match Output unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 15-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
AT90USB64/128 non-PWM modes refer to Table 15-1 on page 137. For fast PWM mode refer to Table 15-2 on page 137, and for phase correct and phase and frequency correct PWM refer to Table 15-3 on page 138. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 15.
Figure 15-6. CTC mode, timing diagram. OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
AT90USB64/128 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values.
AT90USB64/128 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: ( TOP + 1 ) R PCPWM = log ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11).
ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output.
AT90USB64/128 the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
AT90USB64/128 Figure 15-11. Timer/Counter timing diagram, setting of OCFnx, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx value OCRnx OCFnx Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Figure 15-13. Timer/Counter timing diagram, with prescaler (fclk_I/O/8). clk I/O clk Tn (clkI/O /8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx value (update at TOP) New OCRnx value 15.10 16-bit Timer/Counter register description 15.10.1 TCCR1A – Timer/Counter1 Control Register A Bit 15.10.
AT90USB64/128 When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 15-1 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). Table 15-1. Compare Output mode, non-PWM. COMnA1/COMnB1/ COMnC1 COMnA0/COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 Toggle OCnA/OCnB/OCnC on compare match.
Table 15-3. Compare Output mode, phase correct and phase and frequency correct PWM. COMnA1/COMnB/ COMnC1 COMnA0/COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 1 WGM13:0 = 8, 9 10 or 11: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected. 0 Clear OCnA/OCnB/OCnC on compare match when up-counting. Set OCnA/OCnB/OCnC on compare match when counting down.
AT90USB64/128 Waveform Generation mode bit description (1). (Continued) Table 15-4. Mode WGMn3 WGMn2 (CTCn) WGMn1 (PWMn1) WGMn0 (PWMn0) 11 1 0 1 12 1 1 13 1 14 15 Note: 15.10.3 Timer/Counter mode of operation TOP Update of OCRnx at TOVn flag set on 1 PWM, phase correct OCRnA TOP BOTTOM 0 0 CTC ICRn Immediate MAX 1 0 1 (Reserved) – – – 1 1 1 0 Fast PWM ICRn TOP TOP 1 1 1 1 Fast PWM OCRnA TOP TOP 1. The CTCn and PWMn1:0 bit definition names are obsolete.
• Bit 2:0 – CSn2:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 14-8 on page 107 and Figure 14-9 on page 108. Table 15-5. Clock Select bit description. CSn2 CSn1 CSn0 Description 0 0 0 No clock source.
AT90USB64/128 15.10.7 TCNT1H and TCNT1L – Timer/Counter1 Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] 15.10.
15.10.12 OCR3AH and OCR3AL – Output Compare Register 3 A Bit 7 6 5 4 3 2 1 0 OCR3A[15:8] OCR3AH OCR3A[7:0] OCR3AL Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 3 2 1 0 15.10.13 OCR3BH and OCR3BL – Output Compare Register 3 B Bit 7 6 5 4 OCR3B[15:8] OCR3BH OCR3B[7:0] OCR3BL Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 3 2 1 0 15.10.
AT90USB64/128 15.10.17 TIMSK1 – Timer/Counter1 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 – – ICIE1 – OCIE1C OCIE1B OCIE1A TOIE1 Read/write R R R/W R R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TIMSK1 15.10.
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register (ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the counter reaches the TOP value. ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICFn can be cleared by writing a logic one to its bit location.
AT90USB64/128 16. 8-bit Timer/Counter2 with PWM and asynchronous operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • • • • • • • 16.
16.1.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section.
AT90USB64/128 Figure 16-2. Counter unit block diagram. TOVn (int.req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control logic Prescaler T/C oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value.
Figure 16-3. Output Compare unit, block diagram. DATA BUS OCRnx TCNTn = (8-bit comparator) OCFnx (int.req.) top bottom Waveform generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence.
AT90USB64/128 The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 16.
16.5.1 Compare Output mode and Waveform generating The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 16-4 on page 157. For fast PWM mode, refer to Table 16-5 on page 158, and for phase correct PWM refer to Table 16-6 on page 158.
AT90USB64/128 Figure 16-5. CTC mode, timing diagram. OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 16-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 16-6.
AT90USB64/128 generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 16.6.4 Phase correct PWM mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 16-3 on page 157). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output.
AT90USB64/128 Figure 16-9 shows the same timing data, but with the prescaler enabled. Figure 16-9. Timer/Counter timing diagram, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 16-10 shows the setting of OCF2A in all modes except CTC mode. Figure 16-10. Timer/Counter timing diagram, setting of OCF2A, with prescaler (fclk_I/O/8).
Figure 16-11. Timer/Counter timing diagram, clear timer on compare match mode, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 16.8 16.8.
AT90USB64/128 Table 16-2 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 16-2. Compare Output mode, fast PWM mode (1). COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected 0 1 WGM22 = 0: Normal Port Operation, OC0A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match, set OC2A at TOP 1 1 Set OC2A on Compare Match, clear OC2A at TOP Note: Description 1.
Table 16-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode. Compare Output mode, fast PWM mode (1). Table 16-5. COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match, set OC2B at TOP 1 1 Set OC2B on Compare Match, clear OC2B at TOP Note: Description 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP.
AT90USB64/128 Table 16-7. Waveform Generation mode bit description. (Continued) Mode WGM2 WGM1 WGM0 Timer/Counter mode of operation TOP Update of OCRx at TOV flag set on (1)(2) 5 1 0 1 PWM, phase correct OCRA TOP BOTTOM 6 1 1 0 Reserved – – – 7 1 1 1 Fast PWM OCRA TOP TOP Notes: 1. MAX= 0xFF 2. BOTTOM= 0x00 16.8.
• Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 16-8. Table 16-8. 16.8.3 Clock Select bit description.
AT90USB64/128 16.9 16.9.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 16.9.2 Asynchronous operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken.
AT90USB64/128 a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value
16.9.4 TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 – – – – – OCF2B OCF2A TOV2 Read/write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TIFR2 • Bit 2 – OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector.
AT90USB64/128 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2.
17. Output Compare Modulator (OCM1C0A) 17.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers” on page 96 and “8-bit Timer/Counter2 with PWM and asynchronous operation” on page 145.
AT90USB64/128 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 17.2.1 Timing example Figure 17-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 17-3.
18. SPI – Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel AT90USB64/128 and peripheral devices or between several AVR devices.
AT90USB64/128 Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line.
Table 18-1. Pin SPI pin overrides (1). Direction, master SPI Direction, slave SPI MOSI User defined Input MISO Input User defined SCK User defined Input SS User defined Input Note: 1. See “Alternate functions of Port B” on page 79 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
AT90USB64/128 Assembly code example (1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
AT90USB64/128 means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 18.1.
• Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL functionality is summarized in Table 18-2: Table 18-2. CPOL functionality. CPOL Leading edge Trailing edge 0 Rising Falling 1 Falling Rising • Bit 2 – CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK.
AT90USB64/128 corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR). • Bit 6 – WCOL: Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. • Bit 5..
Figure 18-3. SPI transfer format with CPHA = 0. SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 18-4. SPI transfer format with CPHA = 1.
AT90USB64/128 19. USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • • • • • • • • • • • • 19.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is only used by synchronous transfer mode.
AT90USB64/128 19.2.1 Internal Clock Generation – The Baud Rate generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 19-2 on page 178. The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator.
19.2.3 External clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 19-2 on page 178 for details. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver.
AT90USB64/128 A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 19-4 illustrates the possible combinations of the frame formats.
Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed.
AT90USB64/128 den by the USART and given the function as the transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 19.5.1 Sending frames with 5 to 8 data bits A data transmission is initiated by loading the transmit buffer with the data to be transmitted.
a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
AT90USB64/128 UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly code example (1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C code example (1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
AT90USB64/128 Assembly code example (1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
AT90USB64/128 The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 19.6.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost.
Figure 19-5. Start bit sampling. RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
AT90USB64/128 Figure 19-7. Stop bit sampling and next start bit sampling. RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
Table 19-2. Recommended maximum receiver baud rate error for Normal Speed mode (U2Xn = 0). D # (Data+Parity Bit) Rslow [%] Rfast [%] Max. total error [%] Recommended max. receiver error [%] 5 93.20 106.67 +6.67/-6.8 ±3.0 6 94.12 105.79 +5.79/-5.88 ±2.5 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.36 104.58 +4.58/-4.54 ±2.0 9 95.81 104.14 +4.14/-4.19 ±1.5 10 96.17 103.78 +3.78/-3.83 ±1.5 Table 19-3. Recommended maximum receiver baud rate error for Double Speed mode (U2Xn = 1).
AT90USB64/128 with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ister (TXB) will be the destination for data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set. Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmitter.
AT90USB64/128 new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. • Bit 2 – UPEn: USART Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
zero) will not become effective until ongoing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxDn port. • Bit 2 – UCSZn2: Character Size n The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use.
AT90USB64/128 • Bit 3 – USBSn: Stop Bit select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 19-6. USBS bit settings. USBSn Stop bit(s) 0 1-bit 1 2-bit • Bit 2:1 – UCSZn1:0: Character size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. Table 19-7. UCSZn bits settings.
• Bit 15:12 – Reserved bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. • Bit 11:0 – UBRR11:0: USART baud rate register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed.
AT90USB64/128 Table 19-10. Examples of UBRRn settings for commonly used oscillator frequencies. fosc = 3.6864MHz Baud rate [bps] U2Xn = 0 UBRR fosc = 4.0000MHz U2Xn = 1 Error UBRR U2Xn = 0 Error UBRR fosc = 7.3728MHz U2Xn = 1 Error UBRR U2Xn = 0 Error UBRR U2Xn = 1 Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.
Table 19-11. Examples of UBRRn settings for commonly used oscillator frequencies. fosc = 8.0000MHz fosc = 11.0592MHz fosc = 14.7456MHz Baud rate [bps] UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.
AT90USB64/128 Table 19-12. Examples of UBRRn settings for commonly used oscillator frequencies. fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz Baud rate [bps] UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.
20. USART in SPI mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the following features: • • • • • • • • 20.
AT90USB64/128 20.3 BAUD Baud rate (in bits per second, bps) fOSC System oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL registers, (0-4095) SPI data modes and timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 20-1.
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will then signal that the 16-bit value has been shifted out. 20.4.1 USART MSPIM initialization The USART in MSPIM mode has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the Receiver.
AT90USB64/128 Assembly code example (1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writing to the UDRn I/O location. This is the case for both sending and receiving data since the transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame.
AT90USB64/128 20.5.1 Transmitter and receiver flags and interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 20.5.2 Disabling the transmitter or receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation. 20.
20.6.3 UCSRnB – USART MSPIM Control and Status Register n B Bit 7 6 5 4 3 2 1 0 RXCIEn TXCIEn UDRIE RXENn TXENn - - - Read/write R/W R/W R/W R/W R/W R R R Initial value 0 0 0 0 0 1 1 0 UCSRnB • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag.
AT90USB64/128 mal USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled. Table 20-3. UMSELn bits settings. UMSELn1 UMSELn0 Mode 0 0 Asynchronous USART 0 1 Synchronous USART 1 0 (Reserved) 1 1 Master SPI (MSPIM) • Bit 5:3 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use.
• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting UBRRn accordingly • Interrupt timing is not compatible • Pin control differs due to the master only operation of the USART in MSPIM mode A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 20-4 on page 210. Table 20-4. 210 Comparison of USART in MSPIM mode and SPI pins.
AT90USB64/128 21. 2-wire serial interface 21.1 Features • • • • • • • • • • 21.
21.2.2 Electrical interconnection As depicted in Figure 21-1 on page 211, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
AT90USB64/128 Figure 21-3. START, REPEATED START and STOP conditions. SDA SCL STOP START 21.3.3 START REPEATED START STOP Address packet format All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 21-5. Data packet format.
AT90USB64/128 21.4 Multi-master bus systems, arbitration and synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet. Figure 21-8. Arbitration between two masters.
AT90USB64/128 Figure 21-9. Overview of the TWI module. Slew-rate control SDA Spike filter Slew-rate control Spike filter Bus interface unit START / STOP control Spike suppression Arbitration detection Address/data shift register (TWDR) Bit rate generator Prescaler Bit rate register (TWBR) Ack Address match unit Address register (TWAR) Control unit Status register (TWSR) Address comparator Control register (TWCR) State machine and status control TWI unit SCL 21.5.
Note: 21.5.3 TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the Master may produce an incorrect output on SDA and SCL for the reminder of the byte. The problem occurs when operating the TWI in Master mode, sending Start + SLA + R/W to a Slave (a Slave does not need to be connected to the bus for the condition to happen). Bus Interface unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware.
AT90USB64/128 • After the TWI has been addressed by own slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a Slave • When a bus error has occurred due to an illegal START or STOP condition 21.6 21.6.
• Bit 5 – TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted.
AT90USB64/128 Table 21-2. TWI bit rate prescaler. TWPS1 TWPS0 Prescaler value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator unit” on page 217. The value of TWPS1..0 is used in the equation. 21.6.4 TWDR – TWI Data Register Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 1 TWDR In Transmit mode, TWDR contains the next byte to be transmitted.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus. 21.6.6 TWAMR – TWI (Slave) Address Mask Register Bit 7 6 5 4 3 2 1 0 TWAM[6:0] – Read/write R/W R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0 TWAMR • Bits 7..1 – TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask.
AT90USB64/128 Application Action Figure 21-11. Interfacing the application to the TWI in a typical transmission. 1. Application writes to TWCR to initiate transmission of START TWI Hardware Action TWI bus 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, makin sure that TWINT is written to one, and TWSTA is written to zero. START 2. TWINT set. Status code indicates START condition sent SLA+W 5.
The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the packet or not. 7.
AT90USB64/128 (Continued) Assembly code example in ERROR(); andi r16, 0xF8 cpi 3 r16, START brne ERROR ldi r16, SLA_W out TWDR, r16 ldi r16, (1<
S: START condition Rs: REPEATED START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition SLA: Slave Address In Figure 21-13 on page 229 to Figure 21-19 on page 238, circles are used to indicate that the TWINT Flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero.
AT90USB64/128 TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 21-3). In order to enter MT mode, SLA+W must be transmitted.
Table 21-3. 0x20 0x28 0x30 0x38 228 Status codes for Master Transmitter mode.
AT90USB64/128 Figure 21-13. Formats and states in the Master Transmitter mode.
Figure 21-14. Data transfer in Master Receiver mode. VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 1 X 1 0 X 1 0 X TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
AT90USB64/128 Table 21-4. Status code (TWSR) prescaler bits are 0 Status codes for Master Receiver mode.
Figure 21-15. Formats and states in the Master Receiver mode. MR Successfull reception from a slave receiver S SLA R A DATA A $40 $08 DATA A $50 P $58 Next transfer started with a repeated start condition RS SLA R $10 Not acknowledge received after the slave address A W P $48 MT Arbitration lost in slave address or data byte A or A Other master continues A $38 Arbitration lost and addressed as slave A $68 $38 Other master continues $78 A From slave to master 21.8.
AT90USB64/128 The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI.
Table 21-5. Status code (TWSR) prescaler bits are 0 Status codes for Slave Receiver mode.
AT90USB64/128 Figure 21-17. Formats and states in the Slave Receiver mode. Reception of the own slave address and one or more data bytes.
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 Value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
AT90USB64/128 Table 21-6. Status code (TWSR) prescaler bits are 0 0xA8 0xB0 0xB8 0xC0 0xC8 Status codes for Slave Transmitter mode.
Figure 21-19. Formats and states in the Slave Transmitter mode. Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to slave From slave to master 21.8.
AT90USB64/128 Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation.
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit.
AT90USB64/128 22. USB controller 22.1 Features • Support full-speed and low-speed • Support ping-pong mode (dual bank) • 832 bytes of DPRAM: – One endpoint 64 bytes maximum (default control endpoint) – One endpoint of 256 bytes maximum (one or two banks) – Five endpoints of 64 bytes maximum (one or two banks) 22.2 Block diagram The USB controller provides the hardware to interface a USB link to a data flow stored in a double port memory (DPRAM). The USB controller requires a 48MHz ±0.
22.3 Typical application implementation Depending on the USB operating mode (Device only, Reduced Host or OTG mode) and on the target application power supply, the Atmel AT90USB64/128 require different hardware typical implementations. Figure 22-2. Operating modes versus frequency and power-supply. Maximum operating frequency [MHz] VCC (V) 5.5 16MHz 4.5 USB compliant, with internal regulator 3.6 8MHz 3.4 USB compliant, without internal regulator 3.0 2.7 USB not operational 2MHz VCC min 0 22.3.1 22.
AT90USB64/128 Figure 22-4. Typical bus powered application with 3V I/O. External 3V regulator UVCC AVCC VCC UCAP 1µF VBUS VBUS UDP D+ Rs = 22 UDM DRs = 22 UVSS UVSS UGND UID UID XTAL1 22.3.1.2 XTAL2 GND GND Self powered device Figure 22-5. Typical self powered application with 3.4V to 5.5V I/O. External 3.4V - 5.
Figure 22-6. Typical self powered application with 3.0V to 3.6 I/O. External 3.0V - 3.6V power supply UVCC AVCC VCC UCAP 1µF VBUS VBUS UDP D+ Rs = 22 UDM DRs = 22 UVSS UGND UID UID XTAL1 22.3.2 XTAL2 GND GND Host / OTG mode Figure 22-7. Host/OTG application with 3.0V to 3.6 I/O. External 3.0V - 3.
AT90USB64/128 Figure 22-8. Host/OTG application with 5V I/O. External 5.0V power supply 5V UVCC AVCC VCC UCAP 1µF UVCON VBUS VBUS UDP D+ Rs = 22 UDM DRs = 22 UVSS UID UGND UID XTAL1 22.3.
22.4 22.4.1 General operating modes Introduction After a hardware reset, the USB controller is disabled. When enabled, the USB controller has to run the Device Controller or the Host Controller. This is performed using the USB ID detection. • If the ID pin is not connected to ground, the USB ID bit is set by hardware (internal pull up on the UID pad) and the USB Device controller is selected • The ID bit is cleared by hardware when a low level has been detected on the ID pin.
AT90USB64/128 22.4.3 Interrupts Two interrupts vectors are assigned to USB interface. Figure 22-10. USB interrupt system. USB general & OTG interrupt USB device interrupt USB general interrupt vector USB host interrupt Endpoint interrupt USB endpoint/pipe interrupt vector Pipe interrupt See Section 23.17, page 272 and Section 24.15, page 291 for more details on the Host and Device interrupts.
Figure 22-11. USB general interrupt vector sources. IDTI USBINT.1 VBUSTI USBINT.0 STOI OTGINT.5 IDTE USBCON.1 VBUSTE USBCON.0 STOE OTGIEN.5 HNPERRI OTGINT.4 HNPERRE OTGIEN.4 ROLEEXI OTGINT.3 BCERRI OTGINT.2 VBERRI OTGINT.1 SRPI OTGINT.0 UPRSMI UDINT.6 EORSMI UDINT.5 USB general interrupt vector ROLEEXE OTGIEN.3 BCERRE OTGIEN.2 VBERRE OTGIEN.1 SRPE OTGIEN.0 UPRSME UDIEN.6 EORSME UDIEN.5 WAKEUPI UDINT.4 WAKEUPE UDIEN.4 EORSTI UDINT.3 SOFI UDINT.2 SUSPI UDINT.
AT90USB64/128 Figure 22-12. USB endpoint/pipe Interrupt vector sources. Endpoint 6 Endpoint 5 Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 OVERFI UESTAX.6 UNDERFI UESTAX.5 NAKINI UEINTX.6 NAKOUTI UEINTX.4 RXSTPI UEINTX.3 RXOUTI UEINTX.2 FLERRE UEIENX.7 NAKINE UEIENX.6 TXSTPE UEIENX.4 RXSTPE UEIENX.3 Endpoint interrupt EPINT UEINT.X RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
Figure 22-13. USB general and OTG controller interrupt system. IDTI USBINT.1 VBUSTI USBINT.0 STOI OTGINT.5 IDTE USBCON.1 VBUSTE USBCON.0 STOE OTGIEN.5 HNPERRI OTGINT.4 HNPERRE OTGIEN.4 ROLEEXI OTGINT.3 BCERRI OTGINT.2 VBERRI OTGINT.1 SRPI OTGINT.0 USB general & OTG interrupt vector ROLEEXE OTGIEN.3 BCERRE OTGIEN.2 VBERRE OTGIEN.1 Asynchronous interrupt source (allows the CPU to wake up from power down mode SRPE OTGIEN.
AT90USB64/128 • the HWUPI interrupt is triggered in the Host mode (HOST set) • the IDTI interrupt is triggered • the VBUSTI interrupt is triggered 22.5.3 Freeze clock The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the following registers: • USBCON, USBSTA, USBINT • UDCON (detach, ...
22.6.2 Host mode When the USB interface is configured in host mode, internal Pull Down resistors are activated on both UDP UDM lines and the interface detects the type of connected device. 22.7 Memory management The controller does only support the following memory allocation management. The reservation of a Pipe or an Endpoint can only be made in the increasing order (Pipe/Endpoint 0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order.
AT90USB64/128 both Pipe/Endpoint 4 and 5 use a common area. The data of those endpoints are potentially lost Note that: • the data of Pipe/Endpoint 0 are never lost whatever the activation or deactivation of the higher Pipe/Endpoint. Its data is lost if it is deactivated • Deactivate and reactivate the same Pipe/Endpoint with the same parameters does not lead to a “slide” of the higher endpoints.
22.9 OTG timers customizing It is possible to refine some OTG timers thanks to the OTGTCON register that contains the PAGE bits to select the timer and the VALUE bits to adjust the value. User should refer to lastest releases of the OTG specification to select compliant timings. • PAGE=00b: AWaitVrise time-out. [OTG]. In Host mode, once VBUSREQ has been set to “1”, if no VBUS is detected on VBUS pin after this AWaitVrise delay then the VBERRI error flag is set.
AT90USB64/128 22.10 Plug-in detection The USB connection is detected by the VBUS pad, thanks to the following architecture: Figure 22-16. Plug-in detection input block diagram. VDD RPU VBus_pulsing Session_valid VBUS RPU Logic Vbus_valid VBUS VBUSTI USBSTA.0 USBINT.0 VBus_discharge VSS Pad logic The control logic of the VBUS pad outputs a signal regarding the VBUS voltage level: • The “Session_valid” signal is active high when the voltage on the VBUS pad is higher or equal to 1.4V.
22.11 ID detection The ID pin transition is detected thanks to the following architecture: Figure 22-17. ID detection input block diagram. RPU VDD Internal pull up 1 UID ID 0 UIMOD USBSTA.1 UHWCON.7 UIDE UHWCON.6 The ID pin can be used to detect the USB mode (Peripheral or Host) or software selected. This allows the UID pin to be used has general purpose I/O even when USB interface is enable.
AT90USB64/128 • 3-1 – Reserved The value read from these bits is always 0. Do not set these bits. • 0 – UVREGE: USB pad regulator Enable Set to enable the USB pad regulator. Clear to disable the USB pad regulator. Bit 7 6 5 4 3 2 1 0 USBE HOST FRZCLK OTGPADE - - IDTE VBUSTE Read/write R/W R/W R/W R/W R R R/W R/W Initial value 0 0 1 0 0 0 0 0 USBCON • 7 – USBE: USB macro Enable bit Set to enable the USB controller.
• 3 – SPEED: Speed Status Flag This should be read only when the USB controller operates in host mode, in device mode the value read from this bit is undeterminated. Set by hardware when the controller is in FULL-SPEED mode. Cleared by hardware when the controller is in LOW-SPEED mode. • 2 – Reserved The value read from this bit is always 0. Do not set this bit. • 1 – ID: IUD pin flag The value read from this bit indicates the state of the UID pin.
AT90USB64/128 • 4 – SRPREQ: SRP Request bit Set to initiate the SRP when the controller is in Device mode. Cleared by hardware when the controller is initiating a SRP. • 3 – SRPSEL: SRP Selection bit Set to choose VBUS pulsing as SRP method. Clear to choose data line pulsing as SRP method. • 2 – VBUSHWC: VBus Hardware Control bit Set to disable the hardware control over the UVCON pin. Clear to enable the hardware control over the UVCON pin.
Bit 7 6 5 4 3 2 1 0 - - STOE HNPERRE ROLEEXE BCERRE VBERRE SRPE Read/write R R R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OTGIEN • 7-6 - Reserved The value read from these bits is always 0. Do not set these bits. • 5 – STOE: Suspend Time-out Error Interrupt Enable bit Set to enable the STOI interrupt. Clear to disable the STOI interrupt. • 4 – HNPERRE: HNP Error Interrupt Enable bit Set to enable the HNPERRI interrupt. Clear to disable the HNPERRI interrupt.
AT90USB64/128 • 2 – BCERRI: B-Connection Error Interrupt flag Set by hardware when an error occur during the B-Connection (that is, if Peripheral has not connected after 300ms of Vbus delivery request). Shall be cleared by software. • 1 – VBERRI: V-Bus Error Interrupt flag Set by hardware when a drop on VBus has been detected. Shall be cleared by software. • 0 – SRPI: SRP Interrupt flag Set by hardware when a SRP has been detected. Shall be used in the Host mode only. Shall be cleared by software. 22.
23. USB device operating modes 23.1 Introduction The USB device controller supports full speed and low speed data transfers.
AT90USB64/128 • the UEINTX, UESTA0X and UESTA1X are restored to their reset value The data toggle field remains unchanged. The other registers remain unchanged. The endpoint configuration remains active and the endpoint is still enabled. The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as an answer to the CLEAR_FEATURE USB command. 23.
Figure 23-2. Endpoint activation flow. Endpoint Activation UENUM Select the endpoint EPNUM=x EPEN=1 Activate the endpoint UECFG0X Configure: - the endpoint direction - the endpoint type EPDIR EPTYPE ...
AT90USB64/128 ADDEN is cleared by hardware: • after a power-up reset • when an USB reset is received • or when the macro is disabled (USBE cleared) When this bit is cleared, the default device address 00h is used. 23.8 Suspend, wake-up and resume After a period of 3ms during which the USB line was inactive, the controller switches to the fullspeed mode and triggers (if enabled) the SUSPI (suspend) interrupt. The firmware may then set the FRZCLK bit.
23.10 Remote Wake-up The “Remote Wake-up” (or “upstream resume”) request is the only operation allowed to be sent by the device on its own initiative. Anyway, to do that, the device should first have received a DEVICE_REMOTE_WAKEUP request from the host. • First, the USB controller must have detected the “suspend” state of the line: the remote wakeup can only be sent when a SUSPI flag is set • The firmware has then the ability to set RMWKUP to send the “upstream resume” stream.
AT90USB64/128 23.11.2 STALL handshake and retry mechanism The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the STALLRQ request bit is set and if there is no retry required. 23.12 CONTROL endpoint management A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI interrupt is triggered (if enabled). The RXOUTI interrupt is not triggered. The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints.
Figure 23-5. Control read transaction. SETUP USB line DATA SETUP RXSTPI HW IN STATUS IN OUT OUT NAK SW RXOUTI TXINI HW SW HW SW SW Wr Enable HOST Wr Enable CPU A NAK handshake is always generated at the first status stage command. When the controller detect the status stage, all the data writen by the CPU are erased, and clearing TXINI has no effects. The firmware checks if the transmission is complete or if the reception is complete. The OUT retry is always ack’ed.
AT90USB64/128 RXOUTI shall always be cleared before clearing FIFOCON. The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can read data from the bank, and cleared by hardware when the bank is empty. Figure 23-6. Example with 1 and 2 OUT data bank.
23.14.1 Overview The Endpoint must be configured first. The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is composed of multiple banks, this also switches to the next data bank.
AT90USB64/128 If the endpoint uses two banks, the second one can be read by the HOST while the current is being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already ready (free) and TXINI is set immediately. 23.14.2.1 Abort An “abort” stage can be produced by the host in some situations: • In a control transaction: ZLP data OUT received during a IN stage • In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN stage on the IN endpoint • ...
23.16 Overflow In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI interrupt is triggered (if enabled). The packet is acknowledged and the RXOUTI interrupt is also triggered (if enabled). The bank is filled with the first bytes of the packet.
AT90USB64/128 Figure 23-9. USB device controller endpoint interrupt system. Endpoint 6 Endpoint 5 Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 OVERFI UESTAX.6 UNDERFI UESTAX.5 FLERRE UEIENX.7 NAKINI UEINTX.6 NAKINE UEIENX.6 NAKOUTI UEINTX.4 TXSTPE UEIENX.4 RXSTPI UEINTX.3 Endpoint interrupt EPINT UEINT.X TXOUTE UEIENX.3 RXOUTI UEINTX.2 RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.
• 7-3 - Reserved The value read from these bits is always 0. Do not set these bits. • 2 - LSM - USB Device Low Speed Mode selection When configured USB is configured in device mode, this bit allows to select the USB the USB Low Speed or Full Speed Mod. Clear to select full speed mode (D+ internal pull-up will be activate with the ATTACH bit will be set) . Set to select low speed mode (D- internal pull-up will be activate with the ATTACH bit will be set).
AT90USB64/128 • 3 - EORSTI - End Of Reset Interrupt flag Set by hardware when an “End Of Reset” has been detected by the USB controller. This triggers an USB interrupt if EORSTE is set. Shall be cleared by software. Setting by software has no effect. • 2 - SOFI - Start Of Frame Interrupt flag Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1ms). This triggers an USB interrupt if SOFE is set. • 1 - Reserved The value read from this bits is always 0.
• 1 - Reserved The value read from this bits is always 0. Do not set this bit • 0 - SUSPE - Suspend Interrupt Enable Bit Set to enable the SUSPI interrupt. Clear to disable the SUSPI interrupt. Bit 7 6 5 4 3 ADDEN 2 1 0 UADD6:0 UDADDR Read/write W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 • 7 - ADDEN - Address Enable Bit Set to activate the UADD (USB address). Cleared by hardware. Clearing by software has no effect. See Section 23.7, page 264 for more details.
AT90USB64/128 • 3-0 - Reserved The value read from these bits is always 0. Do not set these bits. 23.18.2 USB device endpoint registers Bit 7 6 5 4 3 - - - - - 2 1 0 Read/write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 EPNUM2:0 UENUM • 7-3 - Reserved The value read from these bits is always 0. Do not set these bits. • 2-0 - EPNUM2:0 Endpoint Number bits Load by software to select the number of the endpoint which shall be accessed by the CPU. See Section 23.
• RSTDT - Reset Data Toggle bit Set to automatically clear the data toggle sequence: For OUT endpoint: the next received packet will have the data toggle 0. For IN endpoint: the next packet to be sent will have the data toggle 0. Cleared by hardware instantaneously. The firmware does not have to wait that the bit is cleared. Clearing by software has no effect. • 2 - Reserved The value read from these bits is always 0. Do not set these bits. • 1 - Reserved The value read from these bits is always 0.
AT90USB64/128 Bit 7 6 - 5 4 3 EPSIZE2:0 2 EPBK1:0 1 0 ALLOC - Read/write R R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0 UECFG1X • 7 - Reserved The value read from these bits is always 0. Do not set these bits. • 6-4 - EPSIZE2:0 - Endpoint Size bits Set this bit according to the endpoint size: 000b: 8 bytes 100b: 128 bytes (only for endpoint 1) 001b: 16 bytes 101b: 256 bytes (only for endpoint 1) 010b: 32 bytes 110b: Reserved.
• 6 - OVERFI - Overflow Error Interrupt flag Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt (EPINTx) is triggered (if enabled). See Section 23.15, page 271 for more details. Shall be cleared by software. Setting by software has no effect. • 5 - UNDERFI - Flow Error Interrupt flag Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt (EPINTx) is triggered (if enabled). See Section 23.15, page 271 for more details.
AT90USB64/128 • 2 - CTRLDIR - Control Direction (flag, and bit for debug purpose) Set by hardware after a SETUP packet, and gives the direction of the following packet: - 1 for IN endpoint - 0 for OUT endpoint Can not be set or cleared by software. • 1-0 - CURRBK1:0 - Current Bank (all endpoints except Control endpoint) flag Set by hardware to indicate the number of the current bank: 00b Bank0 01b Bank1 1xb Reserved Can not be set or cleared by software.
• 4 - NAKOUTI - NAK OUT Received Interrupt flag Set by hardware when a NAK handshake has been sent in response of a OUT/PING request from the host. This triggers an USB interrupt if NAKOUTE is sent. Shall be cleared by software. Setting by software has no effect. • 3 - RXSTPI - Received SETUP Interrupt flag Set by hardware to signal that the current bank contains a new valid SETUP packet. An interrupt (EPINTx) is triggered (if enabled). Shall be cleared by software to handshake the interrupt.
AT90USB64/128 • 5 - Reserved The value read from these bits is always 0. Do not set these bits. • 4 - NAKOUTE - NAK OUT Interrupt Enable bit Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set. Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set. • 3 - RXSTPE - Received SETUP Interrupt Enable flag Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent. Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent.
Bit 7 6 5 4 3 2 1 0 BYCT D7 BYCT D6 BYCT D5 BYCT D4 BYCT D3 BYCT D2 BYCT D1 BYCT D0 Read/write R R R R R R R R Initial value 0 0 0 0 0 0 0 0 UEBCLX • 7-0 - BYCT7:0 - Byte Count (low) bits Set by the hardware. BYCT10:0 is: - (for IN endpoint) increased after each writing into the endpoint and decremented after each byte sent, - (for OUT endpoint) increased after each byte sent by the host, and decremented after each byte read by the software.
AT90USB64/128 24. USB host operating modes This mode is available only on Atmel AT90USB647/1287 products. 24.1 Pipe description For the USB Host controller, the term of Pipe is used instead of Endpoint for the USB Device controller. A Host Pipe corresponds to a Device Endpoint, as described in the USB specification. Figure 24-1. Pipes and endpoints in a USB system. In the USB Host controller, a Pipe will be associated to a Device Endpoint, considering the Device Configuration Descriptors. 24.
USB host controller state after an hardware reset is ‘Reset’. When the USB controller is enabled and the USB Host controller is selected, the USB controller is in ‘Idle’ state. In this state, the USB Host controller waits for the Device connection, with a minimum power consumption. The USB Pad should be in Idle mode. The macro does not need to have the PLL activated to enter in ‘Host Ready’ state.
AT90USB64/128 Figure 24-3. Pipe activation flow.
24.7 USB reset The USB controller sends a USB Reset when the firmware set the RESET bit. The RSTI bit is set by hardware when the USB Reset has been sent. This triggers an interrupt if the RSTE has been set. When a USB Reset has been sent, all the Pipe configuration and the memory allocation are reset. The General Host interrupt enable register is left unchanged.
AT90USB64/128 24.12 Control pipe management A Control transaction is composed of three phases: • SETUP • Data (IN or OUT) • Status (OUT or IN) The firmware has to change the Token for each phase. The initial data toggle is set for the corresponding token (ONLY for Control Pipe): • SETUP: Data0 • OUT: Data1 • IN: Data1 (expected data toggle) 24.13 OUT pipe management The Pipe must be configured and not frozen first.
Figure 24-4. Example with OUT data banks.
AT90USB64/128 bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the status of the new bank. Figure 24-5. Example with IN data banks.
Figure 24-7. USB device controller pipe interrupt system. PIPE 6 PIPE 5 PIPE 4 PIPE 3 PIPE 2 PIPE 1 PIPE 0 OVERFI UPSTAX.6 UNDERFI UPSTAX.5 FLERRE UPIEN.7 NAKEDI UPINTX.6 NAKEDE UPIEN.6 PERRI UPINTX.4 PERRE UPIEN.4 TXSTPI UPINTX.3 Pipe interrupt FLERRE UPIEN.7 TXSTPE UPIEN.3 TXOUTI UPINTX.2 TXOUTE UPIEN.2 RXSTALLI UPINTX.1 RXSTALLE UPIEN.1 RXINI UPINTX.0 RXINE UPIEN.0 24.16 Registers 24.16.
AT90USB64/128 Bit 7 6 5 4 3 2 1 0 - HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI Read/write R R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 UHINT • 7 - Reserved The value read from these bits is always 0. Do not set these bits. • 6 - HWUPI - Host Wake-Up Interrupt Set by hardware when a non-idle state is detected on the USB bus.This interrupt should be enable only to wake up the CPU core from power down mode.
• 6 - HWUPE - Host Wake-Up Interrupt Enable Set this bit to enable HWUP interrupt.For correct interrupt handle execution, this interrupt should be enable only before entering power-down mode. Clear this bit to disable HWUP interrupt. • 5 - HSOFE - Host Start Of frame Interrupt Enable Set this bit to enable HSOF interrupt. Clear this bit to disable HSOF interrupt. • 4 - RXRSME -Upstream Resume Received Interrupt Enable Set this bit to enable the RXRSMI interrupt.
AT90USB64/128 Bit 7 6 5 4 3 2 1 0 - - - - - FNUM10 FNUM9 FNUM8 Read/write R R R R R R R R Initial value 0 0 0 0 0 0 0 0 UHFNUMH • 7-4 - Reserved The value read from these bits is always 0. Do not set these bits. • 3-0 - FNUM10:8 - Frame Number The value contained in this register is the current SOF number. This value can be modified by software.
Bit 7 6 5 4 3 2 1 0 - P6RST P5RST P4RST P3RST P2RST P1RST P0RST RW RW RW RW RW RW RW 0 0 0 0 0 0 0 Read/write Initial value 0 UPRST • 7 - Reserved The value read from these bits is always 0. Do not set these bits. • 6 - P6RST - Pipe 6 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 6. • 5 - P5RST - Pipe 5 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 5.
AT90USB64/128 • 5 - INMODE - IN Request mode Set this bit to allow the USB controller to perform infinite IN requests when the Pipe is not frozen. Clear this bit to perform a pre-defined number of IN requests. This number is stored in the UINRQX register. • 4 - Reserved The value read from this bit is always 0. Do not set this bit. • 3 - RSTDT - Reset Data Toggle Set this bit to reset the Data Toggle to its initial value for the current Pipe. Cleared by hardware when proceed.
Bit 7 6 - 5 4 3 PSIZE2:0 2 PBK1:0 1 0 ALLOC - Read/write R RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 UPCFG1X 0 • 7 - Reserved The value read from these bits is always 0. Do not set these bits. • 6-4 - PSIZE2:0 - Pipe Size Select the size of the Pipe: - 000: 8 - 100: 128 (only for endpoint 1) - 001: 16 - 101: 256 (only for endpoint 1) - 010: 32 - 110: Reserved. Do not use this configuration. - 011: 64 - 111: Reserved. Do not use this configuration.
AT90USB64/128 Bit 7 6 5 4 CFGOK OVERFI UNDERFI - Read/write R RW RW Initial value 0 0 0 0 3 2 1 DTSEQ1:0 0 NBUSYBK UPSTAX R R R R 0 0 0 0 • 7 - CFGOK - Configure Pipe Memory OK Set by hardware if the required memory configuration has been successfully performed. Cleared by hardware when the pipe is disabled. The USB reset and the reset pipe have no effect on the configuration of the pipe.
Bit 7 6 5 4 3 2 1 0 INRQ7 INRQ6 INRQ5 INRQ4 INRQ3 INRQ2 INRQ1 INRQ0 Read/write RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 UPINRQX • 7-0 - INRQ7:0 - IN Request Number Before Freeze Enter the number of IN transactions before the USB controller freezes the pipe. The USB controller will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully performed.
AT90USB64/128 Bit 7 6 5 4 3 2 1 0 FIFOCON NAKEDI RWAL PERRI TXSTPI TXOUTI RXSTALLI RXINI Read/write RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 UPINTX • 7 - FIFOCON - FIFO Control For OUT and SETUP Pipe: Set by hardware when the current bank is free, at the same time than TXOUT or TXSTP. Clear to send the FIFO data and to switch the bank. Setting by software has no effect.
• 1 - RXSTALLI / CRCERR - STALL Received / Isochronous CRC Error Set by hardware when a STALL handshake has been received on the current bank of the Pipe. The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. For Isochronous Pipe: Set by hardware when a CRC error occurs on the current bank of the Pipe.
AT90USB64/128 • 0 - RXINE - IN Data received Interrupt Enable Set to enable the RXINI interrupt. Clear to disable the RXINI interrupt. Bit 7 6 5 4 3 2 1 0 PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 Read/write RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 UPDATX • 7-0 - PDAT7:0 - Pipe Data bits Set by the software to read/write a byte from/to the Pipe FIFO selected by PNUM.
25. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
AT90USB64/128 • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
25.1 Analog Comparator multiplexed input It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), and MUX2..
AT90USB64/128 26. ADC – Analog to Digital Converter 26.1 Features • • • • • • • • • • • • • • 26.2 10-bit resolution 0.5 LSB integral non-linearity ±2 LSB absolute accuracy 65 - 260µs conversion time Up to 15ksps at maximum resolution Eight multiplexed single ended input channels Seven differential input channels Optional left adjustment for ADC result readout 0 - VCC ADC input voltage range Selectable 2.
Figure 26-1. Analog to digital converter block schematic. ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADATE ADEN ADSC ADC CTRL.
AT90USB64/128 26.3 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
Figure 26-2. ADC auto trigger logic. ADTS[2:0] PRESCALER START CLKADC ADATE ADIF SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
AT90USB64/128 in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Differential channels” on page 312 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles.
Figure 26-6. ADC timing diagram, auto triggered conversion. One conversion 1 Cycle number 2 3 4 5 6 7 8 9 Next conversion 10 11 12 13 1 2 ADC clock Trigger Source ADATE ADIF ADCH Sign and MSB of result ADCL LSB of result Prescaler reset Sample & hold Prescaler reset Conversion complete MUX and REFS update Figure 26-7. ADC timing diagram, free running conversion.
AT90USB64/128 If differential channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started. Since the stage is dependent of a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are performed.
26.6.1 ADC input channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: • In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC.
AT90USB64/128 a. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine.
26.7.2 Analog noise canceling techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b.
AT90USB64/128 • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB Figure 26-10. Offset error. Output code Ideal ADC Actual ADC Offset error VREF Input voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 26-11. Gain error.
Figure 26-12. Integral non-linearity (INL). Output code INL Ideal ADC Actual ADC VREF Input voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB Figure 26-13. Differential non-linearity (DNL).
AT90USB64/128 For single ended conversion, the result is: V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 26-3 on page 322 and Table 26-4 on page 322). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
Figure 26-14. Differential measurement range.
AT90USB64/128 Table 26-2. Correlation between input voltage and output codes. VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 0.999 VREF /GAIN 0x1FF 511 VADCm + 0.998 VREF /GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF /GAIN 0x3FF -1 ... ... ... VADCm - 0.999 VREF /GAIN 0x201 -511 VADCm - VREF /GAIN 0x200 -512 Example 1: – ADMUX = 0xED (ADC3 - ADC2, 10× gain, 2.
is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. Table 26-3. Voltage reference selections for ADC. REFS1 REFS0 Voltage reference selection 0 0 AREF, internal VREF turned off 0 1 AVCC with external capacitor on AREF pin 1 0 Reserved 1 1 Internal 2.
AT90USB64/128 Table 26-4. MUX4..0 Input channel and gain selections.
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. • Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal.
AT90USB64/128 26.9.3.2 ADLAR = 1 Bit Bit Read/write Initial value 15 14 13 12 11 10 9 8 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 – – – – – – ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form.
Table 26-6. 26.9.5 ADC auto trigger source selections. (Continued) ADTS2 ADTS1 ADTS0 Trigger source 1 0 0 Timer/Counter0 overflow 1 0 1 Timer/Counter1 compare match B 1 1 0 Timer/Counter1 overflow 1 1 1 Timer/Counter1 capture event DIDR0 – Digital Input Disable Register 0 Bit 7 6 5 4 3 2 1 0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DIDR0 • Bit 7:0 – ADC7D..
AT90USB64/128 27. JTAG interface and on-chip debug system 27.0.1 Features • JTAG (IEEE std. 1149.1 compliant) interface • Boundary-scan capabilities according to the IEEE std. 1149.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains) • TDO: Test Data Out. Serial output data from Instruction Register or Data Register The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in reset.
AT90USB64/128 Figure 27-2. TAP controller state diagram. 1 Test-logic-reset 0 0 Run-test/idle 1 Select-DR scan 1 Select-IR scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
AT90USB64/128 • Two single program memory break points + one data memory break point with mask (“range Break Point”) A debugger, like the Atmel AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip debug specific JTAG instructions” on page 331. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port.
27.7 27.7.1 On-chip Debug related Register in I/O memory OCDR – On-chip Debug Register Bit 7 6 5 4 3 2 1 0 MSB/IDRD LSB Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
AT90USB64/128 28. IEEE 1149.1 (JTAG) boundary-scan 28.1 Features • • • • • 28.2 JTAG (IEEE std. 1149.
28.3.1 Bypass register The Bypass register consists of a single Shift register stage. When the Bypass register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. 28.3.2 Device Identification register Figure 28-1 shows the structure of the Device Identification register. Figure 28-1. The Format of the Device Identification register.
AT90USB64/128 Figure 28-2. Reset register. To TDO From other internal and external reset sources From TDI D Q Internal reset ClockDR · AVR_RESET 28.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan chain” on page 337 for a complete description. 28.
The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain • Shift-DR: The IDCODE scan chain is shifted by the TCK input 28.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
AT90USB64/128 28.5.2 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 – – – JTRF WDRF BORF EXTRF PORF Read/write R R R R/W R/W R/W R/W R/W Initial value 0 0 0 See bit description MCUSR • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
Figure 28-3. Boundary-scan cell for bi-directional port pin with pull-up function.
AT90USB64/128 Figure 28-4. General port pin schematic diagram. See Boundary-scan description for details! PUExn PUD Q D DDxn Q CLR RESET OCxn WDx Q Pxn ODxn D PORTxn Q CLR WRx IDxn DATA BUS RDx RESET RRx SLEEP SYNCHRONIZER D D Q RPx Q PINxn L Q Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 28.6.
28.7 Atmel AT90USB64/128 Boundary-scan order Table 28-3 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port Fis scanned in the opposite bit order of the other ports.
AT90USB64/128 Table 28-3. AT90USB64/128 Boundary-scan order. (Continued) Bit number Signal name 61 PD0.Data 60 PD0.Control 59 PD1.Data 58 PD1.Control 57 PD2.Data 56 PD2.Control 55 PD3.Data 54 PD3.Control 53 PD4.Data 52 PD4.Control 51 PD5.Data 50 PD5.Control 49 PD6.Data 48 PD6.Control 47 PD7.Data 46 PD7.Control 45 PE0.Data 44 PE0.Control 43 PE1.Data 42 PE1.Control 41 PC0.Data 40 PC0.Control 39 PC1.Data 38 PC1.Control 37 PC2.Data 36 PC2.Control 35 PC3.
Table 28-3. AT90USB64/128 Boundary-scan order. (Continued) Bit number Signal name 25 PE2.Data 24 PE2.Control 23 PA7.Data 22 PA7.Control 21 PA6.Data 20 PA6.Control 19 PA5.Data 18 PA5.Control 17 PA4.Data 16 PA4.Control 15 PA3.Data 14 PA3.Control 13 PA2.Data 12 PA2.Control 11 PA1.Data 10 PA1.Control 9 PA0.Data 8 PA0.Control 7 PF3.Data 6 PF3.Control 5 PF2.Data 4 PF2.Control 3 PF1.Data 2 PF1.Control 1 PF0.Data 0 PF0.
AT90USB64/128 29. Boot Loader support – read-while-write self-programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 291 and Figure 29-1 on page 345.
AT90USB64/128 Figure 29-1. Read-While-Write vs. no Read-While-Write. Read-While-Write (RWW) section Z-pointer Addresses RWW section Z-pointer addresses NRWW section No Read-While-Write (NRWW) section CPU is halted during the operation Code located in NRWW section.
Figure 29-2. Memory sections.
AT90USB64/128 Table 29-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
Table 29-4. BOOTRST Note: 29.5.3 Boot reset fuse (1). Reset address 1 Reset Vector = Application reset (address 0x0000) 0 Reset Vector = Boot loader reset (see Table 29-8 on page 357) 1. “1” means unprogrammed, “0” means programmed. External hardware conditions The Hardware Boot Enable Fuse (HWBE) can be programmed (see Table 29-5) so that upon special hardware conditions under reset, the boot loader execution is forced after reset. Table 29-5. HWBE Note: Hardware boot enable fuse (1).
AT90USB64/128 29.5.4 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
• Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
AT90USB64/128 Figure 29-4. Addressing the flash during SPM (1). BIT 23 ZPCMSB ZPAGEMSB 1 0 0 PCMSB PROGRAM COUNTER Z - POINTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 29.7 1. The different variables used in Figure 29-4 are listed in Table 29-10 on page 358. Self-programming the flash The program memory is updated in a page by page fashion.
page. See “Simple Assembly Code example for a Boot Loader” on page 355 for an assembly code example. 29.7.1 Performing page erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
AT90USB64/128 as described in “Interrupts” on page 68, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code example for a Boot Loader” on page 355 for an example. 29.7.7 Setting the Boot Loader Lock bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table 30-4 on page 361 for detailed description and mapping of the Fuse High byte.
AT90USB64/128 the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
ldi loophi, high(PAGESIZEB) Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcsrval, (1<
AT90USB64/128 Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence out SPMCSR, spmcsrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret Atmel AT90USB64/128 Boot Loader parameters In Table 29-8 through Table 29-10 on page 358, the parameters used in the description of the self-programming are given.
Table 29-10. Explanation of different variables used in Figure 29-4 on page 351 and the mapping to the Z-pointer. Corresponding Z-value Variable Description (1) PCMSB 16 Most significant bit in the Program Counter. (The Program Counter is 17 bits PC[16:0]) PAGEMSB 6 Most significant bit which is used to address the words within one page (128 words in a page requires seven bits PC [6:0]). ZPCMSB Z17 Bit in Z-pointer that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
AT90USB64/128 30. Memory programming 30.1 Program and data memory lock bits The Atmel AT90USB64/128 provides six Lock bits, which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 30-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 30-1. Lock Bit byte (1). Lock bit byte Bit no.
Lock bit protection modes (1)(2). (Continued) Table 30-2. Memory lock bits Protection type BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
AT90USB64/128 Table 30-4. Fuse High Byte (AT90USB128: 0x99 - AT90USB64: 0x9B). Fuse high byte Bit no. Description Default value 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN (1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 30.3 Signature bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. Atmel AT90USB128x Signature Bytes: 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x97 (indicates 128KB Flash memory). 3.
AT90USB64/128 Figure 30-1. Parallel programming (1). +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12V VCC +5V AVCC DATA PB7 - PB0 RESET BS2 PA0 XTAL1 GND Note: 1. Unused pins should be left floating. Table 30-6. Pin name mapping.
Table 30-8. Pin values used to enter programming mode. Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 30-9. XA1 and XA0 enoding. XA1 XA0 Action when XTAL1 is pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS2 and BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 30-10. Command byte bit encoding.
AT90USB64/128 Table 30-12. No. of words in a page and no. of pages in the EEPROM. 30.6 30.6.1 EEPROM size Page size PCWORD No. of pages PCPAGE EEAMSB 1kBytes 4 bytes EEA[2:0] 256 EEA[9:3] 9 2kBytes 8 bytes EEA[2:0] 256 EEA[10:3] 10 4kBytes 8 bytes EEA[2:0] 512 EEA[11:3] 11 Parallel programming Enter programming mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times.
30.6.4 Programming the Flash The Flash is organized in pages, see Table 30-11 on page 364. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse.
AT90USB64/128 3. Set DATA = Address extended high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. I. Program Page 1. Set BS2, BS1 to “00” 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3. Wait until RDY/BSY goes high (see Figure 30-3 on page 368 for signal waveforms). J. Repeat B through I until the entire Flash is programmed or until all data has been programmed. K. End Page Programming 1. 1. Set XA1, XA0 to “10”.
Figure 30-3. Programming the Flash waveforms (1). F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G H ADDR. HIGH ADDR. EXT.H I XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL Note: 30.6.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 30-12 on page 365.
AT90USB64/128 Figure 30-4. Programming the EEPROM waveforms. K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C E DATA XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 30.6.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 366 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. H: Load Address Extended Byte (0x00- 0xFF). 3.
30.6.9 Programming the Fuse High bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 366 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS2, BS1 to “01”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2, BS1 to “00”. This selects low data byte. 30.6.
AT90USB64/128 30.6.12 Reading the Fuse and Lock bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 366 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, and BS2, BS1 to “10”.
30.6.15 Parallel programming characteristics Figure 30-7. Parallel programming timing, including some general timing requirements. tXLWL tXHXL XTAL1 tDVXH tXLDX Data & control (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 30-8. Parallel programming timing, loading sequence with timing requirements (1).
AT90USB64/128 Note: 1. The timing requirements shown in Figure 30-7 (that is, tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 30-13. Parallel programming characteristics, VCC = 5V ±10%. Symbol Parameter Min. VPP Programming Enable Voltage 11.
30.8 Serial programming pin mapping Table 30-14. Pin mapping serial programming. Symbol Pins (TQFP-64) I/O Description PDI PB2 I Serial Data in PDO PB3 O Serial Data out SCK PB1 I Serial Clock Figure 30-10. Serial programming and verify (1). +1.8 - 5.5V VCC +1.8 - 5.5V(2) PDI AVCC PDO SCK XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.
AT90USB64/128 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time.
Table 30-16. Serial programming instruction set. Instruction format Instruction Programming Enable Chip Erase Byte 1 Byte 2 Byte 3 Byte 4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0100 1101 0000 0000 cccc cccc xxxx xxxx Defines Extended Address Byte for Read Program Memory and Write Program Memory Page.
AT90USB64/128 Table 30-16. Serial programming instruction set. (Continued) Instruction format Instruction Byte 1 Byte 2 Byte 3 Byte 4 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. See Table 30-3 on page 360 for details. 0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is still busy.
Figure 30-12. State machine sequence for changing the instruction word. 1 Test-logic-reset 0 0 Run-test/idle 1 Select-DR scan 1 Select-IR scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 30.9.2 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
AT90USB64/128 30.9.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register.
30.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register.
AT90USB64/128 Figure 30-14. Programming Command register.
Table 30-17. JTAG programming instruction set. a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
AT90USB64/128 Table 30-17. JTAG programming instruction set. (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence Notes 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c.
Table 30-17. JTAG programming instruction set. (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence 8d. Read Fuse Low Byte (8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. Read Lock Bits (9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f.
AT90USB64/128 Figure 30-15. State machine sequence for changing/reading the data word. 1 Test-logic-reset 0 0 Run-test/idle 1 Select-DR scan 1 Select-IR scan 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 30.9.
ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 30-16. Flash Data Byte Register.
AT90USB64/128 30.9.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 30-13 on page 373). 30.9.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 387. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3.
1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b, 3c and 3d. PCWORD (refer to Table 30-11 on page 364) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5.
AT90USB64/128 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 30-13 on page 373). 30.9.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b.
31. Electrical characteristics for Atmel AT90USB64/128 31.1 Absolute maximum ratings* Operating temperature..................................... -40°C to +85°C *NOTICE: Storage temperature...................................... -65°C to +150°C Voltage on any pin except RESET and VBUS with respect to ground (7) .............................-0.5V to VCC+0.5V Voltage on RESET with respect to ground ......-0.5V to +13.
AT90USB64/128 TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted). (Continued) Symbol ICC Icc Parameter Power Supply Current Typ. Max. (5) Active 4MHz, VCC = 3V (AT90USB64/128) 2.
7. As specified on the USB Electrical chapter of USB Specifications 2.0, the D+/D- pads can withstand voltages down to -1V applied through a 39Ω resistor 8. USB Peripheral consumes up to 50mA from the regulator or UVCC pin when USB is used at full-load 31.3 External clock drive waveforms Figure 31-1. External clock drive waveforms. V IH1 V IL1 31.4 External clock drive Table 31-1. VCC=1.8-5.5V VCC=2.7-5.5V VCC=4.5-5.5V Symbol Parameter Min. Max. Min. Max. Min. Max.
AT90USB64/128 Figure 31-2. Maximum frequency vs. VCC, Atmel AT90USB64/128. 16MHz 8MHz 31.6 2-wire serial interface characteristics Table 31-2 describes the requirements for devices connected to the 2-wire Serial Bus. The AT90USB64/128 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 31-3 on page 394. Table 31-2. 2-wire serial bus requirements. Symbol Parameter VIL VIH (1) (1) Ii Ci -0.5 0.3 VCC Input High-voltage 0.
Table 31-2. 2-wire serial bus requirements. (Continued) Symbol Parameter tHD;STA Hold Time (repeated) START Condition tLOW Low Period of the SCL Clock tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: Condition Min Max fSCL ≤ 100kHz 4.0 – fSCL > 100kHz 0.6 – (6) 4.7 – fSCL > 100kHz (7) 1.
AT90USB64/128 31.7 SPI timing characteristics See Figure 31-4 and Figure 31-5 on page 396 for details. Table 31-3. SPI timing parameters. Description Mode 1 SCK period Master See Table 18-4 on page 174 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 31-5. SPI interface timing requirements (slave mode). SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data input) 14 12 MSB ... LSB 17 15 MISO (Data output) 31.8 MSB ... LSB X Hardware boot entrance timing characteristics Figure 31-6. Hardware boot timing requirements. RESET tSHRH tHHRH ALE/HWB Table 31-4. 396 Hardware boot timings. Symbol Parameter tSHRH HWB low Setup before Reset High tHHRH HWB low Hold after Reset High Min. Max.
AT90USB64/128 31.9 ADC characteristics Table 31-5. Symbol ADC characteristics. Parameter Resolution Condition Min. Typ. Single Ended Conversion 10 Differential Conversion Gain = 1× or 10× 8 Differential Conversion Gain = 200× 7 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz Max. Units Bits 1.
Table 31-5. Symbol ADC characteristics. (Continued) Parameter AVCC Analog Supply Voltage VREF Reference Voltage VIN Condition Min. Typ. Max. VCC - 0.3 VCC + 0.3 Single Ended Conversion 2.0 AVCC Differential Conversion 2.0 AVCC - 0.5 Single ended channels 0 VREF Differential Conversion 0 AVCC Input Voltage Single Ended Channels Units V 38,5 Input Bandwidth kHz Differential Channels 4 VINT1 Internal Voltage Reference 1.1V 1.0 1.1 1.2 VINT2 Internal Voltage Reference 2.
AT90USB64/128 31.10 External data memory timing Table 31-6. External data memory characteristics, 4.5 - 5.5 Volts, no wait-state. 8MHz oscillator Min. Max. Variable oscillator Symbol Parameter 0 1/tCLCL Oscillator Frequency 1 tLHLL ALE Pulse Width 115 1.0tCLCL-10 2 tAVLL Address Valid A to ALE Low 57.5 0.5tCLCL-5 (1) 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 4 tAVLLC Address Valid C to ALE Low 57.5 0.
Table 31-8. External data memory characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0. 4MHz oscillator Symbol Parameter 0 1/tCLCL Oscillator Frequency 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 15 tDVWH Data Valid to WR High 375 3.0tCLCL 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 Table 31-9. Min. Max. Variable oscillator Min. Max. Unit 0.0 16 MHz 325 3.0tCLCL-50 ns External data memory characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1.
AT90USB64/128 Table 31-10. External data memory characteristics, 2.7 - 5.5 Volts, no wait-state. (Continued) 4MHz oscillator Symbol Parameter Min. 12 tRLRH RD Pulse Width 235 1.0tCLCL-15 13 tDVWL Data Setup to WR Low 105 0.5tCLCL-20 (1) 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 15 tDVWH Data Valid to WR High 250 1.0tCLCL 16 tWLWH WR Pulse Width 235 1.0tCLCL-15 Notes: Max. Variable oscillator Min. Max. Unit ns 1. This assumes 50% clock duty cycle.
Figure 31-7. External memory timing (SRWn1 = 0, SRWn0 = 0. T1 T2 T3 T4 System clock (CLK CPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) 11 Data 5 Read Address 10 8 12 RD Figure 31-8. External memory timing (SRWn1 = 0, SRWn0 = 1). T1 T2 T3 T4 T5 System clock (CLK CPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 DA7:0 Prev.
AT90USB64/128 Figure 31-9. External memory timing (SRWn1 = 1, SRWn0 = 0). T1 T2 T3 T5 T4 T6 System clock (CLK CPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 Prev. data Address XX Data 14 16 6 Write DA7:0 13 3a 2 WR 9 3b DA7:0 (XMBK = 0) Address 11 5 Read Data 10 8 12 RD Figure 31-10. External memory timing (SRWn1 = 1, SRWn0 = 1). T1 T2 T3 T4 T6 T5 T7 System clock (CLK CPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev.
32. Atmel AT90USB64/128 typical characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
AT90USB64/128 32.1 Input voltage levels Figure 32-1. Input low voltage vs. VCC, all I/Os excluding DP/DM, XTAL1 and reset. 1.75 Thre s hold (V) 1.50 1.25 85 1.00 -40 25 0.75 0.50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC (V) Figure 32-2. Input high voltage vs. VCC, all I/Os excluding DP/DM, XTAL1 and reset. 1.75 Thre s hold (V) 1.50 1.25 85 1.00 -40 25 0.75 0.50 2.5 3.0 3.5 4.0 4.5 5.0 5.
32.2 Output voltage levels Figure 32-3. Output low voltage vs. output current, all I/Os excluding DP/DM, VCC = 3V. 1.2 1.0 V OL (V) 0.8 85 25 0.6 -40 0.4 0.2 0 0 5 10 15 20 IOL (mA) Figure 32-4. Output low voltage vs. output current, all I/Os excluding DP/DM, VCC = 5V. 0.7 0.6 V OL (V) 0.5 85 0.4 25 0.3 -40 0.2 0.
AT90USB64/128 Figure 32-5. Output high voltage vs. output current, all I/Os excluding DP/DM, VCC = 3V. 3.0 2.8 V OH (V) 2.6 85 25 2.4 -40 2.2 2.0 1.8 0 5 10 15 20 IOH (mA) Figure 32-6. Output high voltage vs. output current, all I/Os excluding DP/DM, VCC = 5V. 5.0 V OH (V) 4.8 85 25 4.6 -40 4.4 4.
32.3 Power-down supply current Figure 32-7. Power-down supply current vs. VCC, with BOD disabled, WDT disabled, T = 25°C. 3.0 2.5 ICC (µA) 2.0 1.5 1.0 0.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC (V) Figure 32-8. Power-down supply current vs. VCC, with BOD disabled, WDT enabled, T = 25°C. 16 14 12 ICC (µA) 10 8 6 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.
AT90USB64/128 Figure 32-9. Power-down supply current vs. VCC, with BOD enabled, WDT enabled, T = 25°C. 60 50 ICC (µA) 40 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC (V) 32.4 Power-save supply current Figure 32-10. Power-save supply current vs. VCC, with BOD & WDT disabled, T = 25°C. 8 7 6 ICC (µA) 5 4 3 2 1 0 2.5 3.0 3.5 4.0 4.5 5.0 5.
32.5 Idle supply current Figure 32-11. Idle supply current vs. frequency, T = 25°C. 20 ICC (mA) 15 10 5.5 5.0 4.5 5 3.3 2.7 0 2 4 6 8 10 12 14 16 Fre que nc y (MHz ) 32.6 Active supply current Figure 32-12. Active supply current vs. frequency, T = 25°C. 25 ICC (mA) 20 15 5.5 5.0 10 4.5 3.3 5 2.
AT90USB64/128 32.7 Reset supply current Figure 32-13. Reset supply current vs. frequency. 12 10 ICC (mA) 8 6 5.5 5.0 4 4.5 3.3 2 2.7 0 4 6 8 10 12 14 16 Fre que nc y (MHz ) 32.8 I/O pull-up current Figure 32-14. I/O pull-up current vs. pin voltage, VCC = 5V.
Figure 32-15. Reset pull-up current vs. pin voltage, VCC = 5V. 120 100 IRES ET (µA) 80 85 60 25 -40 40 20 0 0 1 2 3 4 5 V RE S E T (V) 32.9 Bandgap voltage Figure 32-16. Bandgap voltage vs. temperature. 1.115 Bandgap voltage (V) 1.110 1.105 1.100 5.5 1.095 5.0 4.5 1.090 4.0 3.6 1.085 1.080 -40 2.
AT90USB64/128 32.10 Internal ARef voltage Figure 32-17. Internal ARef reference voltage vs. temperature, VCC = 2.7-5.5V. Tens ion Vref Inter (V) 2.64 2.62 2.60 2.58 2.56 2.54 -40 -20 0 20 40 60 80 Te mpe ra ture (°C) 32.11 USB regulator Figure 32-18. USB regulator quiescent current vs. input voltage, no load. 100 90 80 70 ICC (µA) 60 50 40 30 20 10 0 3.0 3.5 4.0 4.5 5.0 5.5 6.
Figure 32-19. USB regulator output voltage vs. input voltage, load = 75Ω. 3.4 Output voltage (V) 3.2 85 25 3.0 -40 2.8 2.6 3.0 3.5 4.0 4.5 5.0 5.5 Input Volta ge (V) Note: The 75Ω load is equivalent to the maximum average consumption of the USB peripheral in operation (full bus load). 32.12 BOD levels Figure 32-20. BOD voltage (2.4V level) vs. temperature. 2.54 Thres hold (V) 2.52 2.50 Rising Vcc 2.48 Falling Vcc 2.46 2.44 2.
AT90USB64/128 Figure 32-21. BOD voltage (3.4V level) vs. temperature. 3.56 3.54 Thres hold (V) 3.52 3.50 Rising Vcc Falling Vcc 3.48 3.46 3.44 3.42 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Te mpe ra ture (°C) Figure 32-22. BOD voltage (4.3V level) vs. temperature. 4.50 4.48 Thres hold (V) 4.46 4.44 Rising Vcc 4.42 Falling Vcc 4.40 4.38 4.36 4.
32.13 Watchdog timer frequency Figure 32-23. WDT oscillator frequency vs. VCC. 124 122 FRC (kHz) 120 118 85 25 116 -40 114 112 110 108 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC (V) 32.14 Internal RC oscillator frequency Figure 32-24. RC oscillator frequency vs. OSCCAL, T = 25°C.
AT90USB64/128 Figure 32-25. RC oscillator frequency vs. VCC. 8.8 8.7 8.6 FRC (MHz) 8.5 8.4 85 8.3 25 8.2 -40 8.1 8.0 7.9 7.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC (V) Figure 32-26. RC oscillator frequency vs. temperature. 8.8 FRC (MHz) 8.6 8.4 5.5 4.0 8.2 3.3 3.0 8.0 2.7 7.
32.15 Power-on reset Figure 32-27. Power-on reset level vs. temperature. 1.7 1.6 POR Voltage (V) 1.5 1.4 1.3 1.2 1.1 1.
AT90USB64/128 33.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 420 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 (0xB8) TWBR (0xB7) Reserved - - - - - - - - (0xB6) ASSR - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB
AT90USB64/128 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 (0x7B) ADCSRB ADHSM ACME - - - ADTS2 ADTS1 ADTS0 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH (0x78) ADCL (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) XMCRB XMBK - - - - XMM2 XMM1 XMM0 (0x74) XMCRA SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 (0x73
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1B (0x3B) PCIFR - - - - - - - PCIF0 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) TIFR3 - - ICF3 - OCF3C OCF3B OCF3A TOV3 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 0x16 (0x36) TIFR1 - - ICF1 - OCF1C OCF1B OCF1A TOV1 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reser
AT90USB64/128 34.
Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), R
AT90USB64/128 Mnemonics Operands SPM IN Rd, P Description Operation Flags Store Program Memory (Z) ← R1:R0 None #Clocks - In Port Rd ← P None 1 1 OUT P, Rr Out Port P ← Rr None PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
35. Ordering information 35.1 Atmel AT90USB646 Speed [MHz] Power supply [V] Ordering code (2) USB interface Package (1) Operating range 16 (3) 2.7-5.5 AT90USB646-AU AT90USB646-MU Device MD PS Industrial (-40° to +85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European directive for Restriction of Hazardous Substances (RoHS directive).
AT90USB64/128 35.2 Atmel AT90USB647 Speed [MHz] Power supply [V] Ordering code (2) USB interface Package (1) Operating range 16 (3) 2.7-5.5 AT90USB647-AU AT90USB647-MU USB OTG MD PS Industrial (-40° to +85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European directive for Restriction of Hazardous Substances (RoHS directive).
35.3 Atmel AT90USB1286 Speed [MHz] Power supply [V] Ordering code (2) USB interface Package (1) Operating range 16 (3) 2.7-5.5 AT90USB1286-AU AT90USB1286-MU Device MD PS Industrial (-40° to +85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European directive for Restriction of Hazardous Substances (RoHS directive).
AT90USB64/128 35.4 Atmel AT90USB1287 Speed [MHz] Power supply [V] Ordering code (2) USB interface Package (1) Operating range 16 (3) 2.7-5.5 AT90USB1287-AU AT90USB1287-MU Host (OTG) MD PS Industrial (-40° to +85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European directive for Restriction of Hazardous Substances (RoHS directive).
36. Packaging information 36.
AT90USB64/128 431 7593L–AVR–09/12
36.
AT90USB64/128 433 7593L–AVR–09/12
37. Errata 37.1 Atmel AT90USB1287/6 errata 37.1.
AT90USB64/128 not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300µA extra-power consumption. Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit). Problem fix/workaround USB waiver allows bus powered devices to consume up to 2.5mA in suspend state. 6.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep again it may wake up multiple times. Problem fix/workaround A s o f t wa r e w o r k a r o u n d i s t o wa i t w i t h p e r f o r m i n g t h e s l e e p i n s t r u c t i o n u n t i l TCNT2>OCR2+1.
AT90USB64/128 37.1.3 Atmel AT90USB1287/6 second release • Incorrect CPU behavior for VBUSTI and IDTI interrupts routines • USB Eye Diagram violation in low-speed mode • Transient perturbation in USB suspend mode generates over consumption • VBUS Session valid threshold voltage • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 7.
Problem fix/workaround No known workaround, enable Atmel AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1.
AT90USB64/128 37.1.4 Atmel AT90USB1287/6 Third Release • Incorrect CPU behavior for VBUSTI and IDTI interrupts routines • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 5.
Problem fix/workaround A software workaround is to wait before performing the sleep instruction: until TCNT2>OCR2+1.
AT90USB64/128 37.1.5 Atmel AT90USB1287/6 Fourth Release • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 4. Transient perturbation in USB suspend mode generates overconsumption In device mode and when the USB is suspended, transient perturbation received on the USB lines generates a wake up state.
37.2 37.2.1 Atmel AT90USB646/7 errata AT90USB646/7 errata history TBD Silicon Release 90USB646-16MU 90USB647-16AU 90USB647-16MU First Release Second Release Note ‘*’ means a blank or any alphanumeric string. 37.2.2 AT90USB646/7 first release.
AT90USB64/128 Problem fix/workaround No known workaround, enable Atmel AT90USB64/128 TWI first versus the others nodes of the TWI network. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1.
37.2.3 Atmel AT90USB646/7 Second Release. • USB Eye Diagram violation in low-speed mode • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple interrupts 5. USB Eye Diagram violation in low-speed mode The low to high transition of D- violates the USB eye diagram specification when transmitting with low-speed signaling. Problem fix/workaround None. 4.
AT90USB64/128 38. Datasheet revision history for Atmel AT90USB64/128 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 38.1 Changes from 7593A to 7593B 1. Changed default configuration for fuse bytes and security byte. 2. Suppression of timer 4,5 registers which does not exist. 3. Updated typical application schematics in USB section 38.2 Changes from 7593B to 7593C 1.
7. Added description to access unique serial number located in Signature Row see “Reading the Signature Row from software” on page 354. 38.8 Changes from 7593H to 7593I 1. Updated Table 9-2 in “Brown-out detection” on page 60. Unused BOD levels removed. 38.9 Changes from 7593I to 7593J 1. Updated Table 9-2 in “Brown-out detection” on page 60. BOD level 100 removed. 2. Updated “Ordering information” on page 426. 3. Removed ATmega32U6 errata section. 38.10 Changes from 7593J to 7593K 1.
AT90USB64X/128X Table of contents Features ..................................................................................................... 1 1 Pin configurations ................................................................................... 3 2 Overview ................................................................................................... 5 2.1 Block diagram ..........................................................................................................6 2.
7.10 PLL ......................................................................................................................49 8 Power management and sleep modes ................................................. 51 8.1 Idle mode ...............................................................................................................52 8.2 ADC noise reduction mode ...................................................................................52 8.3 Power-down mode .............................
AT90USB64X/128X 14.2 Timer/Counter clock sources ...............................................................................99 14.3 Counter unit .........................................................................................................99 14.4 Output compare unit ..........................................................................................100 14.5 Compare Match Output Unit ..............................................................................102 14.
19 USART ................................................................................................... 177 19.1 Overview ...........................................................................................................177 19.2 Clock generation ...............................................................................................178 19.3 Frame formats ...................................................................................................180 19.4 USART initialization .....
AT90USB64X/128X 22.6 Speed control ....................................................................................................251 22.7 Memory management .......................................................................................252 22.8 PAD suspend ....................................................................................................253 22.9 OTG timers customizing ....................................................................................254 22.
24.8 Address setup ...................................................................................................288 24.9 Remote wake-up detection ................................................................................288 24.10 USB pipe reset ................................................................................................288 24.11 Pipe data access .............................................................................................288 24.12 Control pipe management .....
AT90USB64X/128X 28.4 Boundary-scan specific JTAG instructions ........................................................335 28.5 Boundary-scan Related Register in I/O memory ...............................................336 28.6 Boundary-scan chain .........................................................................................337 28.7 Atmel AT90USB64/128 Boundary-scan order ...................................................340 28.8 Boundary-scan description language files .........................
32.1 Input voltage levels ............................................................................................405 32.2 Output voltage levels .........................................................................................406 32.3 Power-down supply current ...............................................................................408 32.4 Power-save supply current ................................................................................409 32.5 Idle supply current ................
AT90USB64X/128X 38.6 Changes from 7593F to 7593G .........................................................................445 38.7 Changes from 7593G to 7593H ........................................................................445 38.8 Changes from 7593H to 7593I ..........................................................................446 38.9 Changes from 7593I to 7593J ...........................................................................446 38.10 Changes from 7593J to 7593K ....................
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