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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 32 (7x7) 8-Bit 16 MHz I/O number 27
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AT90PWM216/316 [DATASHEET]
7710HS–AVR–07/2013
9. Datasheet Revision History for AT90PWM216/316
Please note that the referring page numbers in this section are referred to this document. The referring revision in
this section are referring to the document revision.
9.1 Rev. 7710H – 07/2013
9.2 Rev. 7710G – 03/2013
1. Removed “1. History” chapter.
2. Errata:
“Revision C” on page 23: Errata added.
“Revision B” on page 23: Errata added.
“Revision A” on page 24: Errata updated.
1. Applied the Atmel new brand template that includes new logo and new addresses.
2. Added note to the MLF/QFN package: The Center GND PADDLE has to be connected to GND.
3. Updated the Figure 2-1 on page 3. Pin 18 changed to AGND instead of GND.
4. Updated the Figure 2-2 on page 4. Pin 24 changed to AGND instead of GND.
5. Added note to the MLF/QFN package: The Center GND PADDLE has to be connected to GND.
6. Updated Figure 5-2 on page 18.
7. Updated Table 6-2 on page 26.
8. Updated “MCU Control Register – MCUCR” on page 62. Added link for Bit 4:
“Configuring the Pin” on page 57.
9. Corrected “typos” in “Overview” on page 122.
10. Updated “Features” on page 122. Correct feature is: Abnormality protection function, emergency input to force
all outputs to low level.
11. Updated “Center Aligned Mode” on page 130. The label PSCn00 and PSCn01 are incorrect and are respectively
replaced by PSCn0 and PSCn1.
12. Updated the formula of “The waveform frequency is defined by the following equation” in “Normal Mode”
on page 134.
13. Updated the formula of f
AVERAGE
in “Enhanced Mode” on page 135.
14. Updated “Input Mode Operation” on page 140. Added a link to the Table 15-6.
15. Updated “PSC Synchronization” on page 151. The correct content: If the PSCn has its PARUNn bit set, then it can
start at the same time as PSCn-1.
16. Updated “PSC 1 Control Register – PCTL1” on page 158. Bit 4 and Bit 3 linked to “PSC Input Configuration” on
page 139.
17. Updated content description of Bit 1 and Bit 3 in “PSC 2 Synchro and Output Configuration – PSOC2” on page 154.
18. Updated “Output Compare SA Register – OCRnSAH and OCRnSAL” on page 155 and “Output Compare RB
Register – OCRnRBH and OCRnRBL” on page 155. The registers are R/W and not only W.
19.
20. Updated “Overview” on page 215. Removed “or CLKi/O/2” from the overview description.
21. Updated Figure 19-1 on page 216, “Analog Comparator Block Diagram(1)(2)” .