Datasheet

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4317K–AVR–03/2013
AT90PWM2/3/2B/3B
7.9 Clock Output Buffer 38
7.10 System Clock Prescaler 38
8 Power Management and Sleep Modes 41
8.1 Sleep Mode Control Register – SMCR 41
8.2 Idle Mode 41
8.3 ADC Noise Reduction Mode 42
8.4 Power-down Mode 42
8.5 Standby Mode 42
8.6 Power Reduction Register 43
8.7 Minimizing Power Consumption 44
9 System Control and Reset 46
9.1 Internal Voltage Reference 50
9.2 Watchdog Timer 52
10 Interrupts 57
10.1 Interrupt Vectors in AT90PWM2/2B/3/3B 57
11 I/O-Ports 62
11.1 Introduction 62
11.2 Ports as General Digital I/O 62
11.3 Alternate Port Functions 67
11.4 Register Description for I/O-Ports 80
12 External Interrupts 82
13 Timer/Counter0 and Timer/Counter1 Prescalers 84
13.1 Internal Clock Source 84
13.2 Prescaler Reset 84
13.3 External Clock Source 84
13.4 General Timer/Counter Control Register – GTCCR 85
14 8-bit Timer/Counter0 with PWM 87
14.1 Overview 87
14.2 Timer/Counter Clock Sources 88
14.3 Counter Unit 88
14.4 Output Compare Unit 89
14.5 Compare Match Output Unit 91
14.6 Modes of Operation 92
14.7 Timer/Counter Timing Diagrams 96