Datasheet

251
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
21.8.4 ADC Result Data Registers – ADCH and ADCL
When an ADC conversion is complete, the conversion results are stored in these two result data
registers.
When the ADCL register is read, the two ADC result data registers can’t be updated until the
ADCH register has also been read.
Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the
result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read
ADCH to have the conversion result.
21.8.4.1 ADLAR = 0
21.8.4.2 ADLAR = 1
21.8.5 Digital Input Disable Register 0 – DIDR0
1 0 1 0 PSC2ASY Event
(1)
1011Reserved
1100Reserved
1101Reserved
1110Reserved
1111Reserved
1. For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock
source.
Table 21-7. ADC Auto Trigger Source Selection for amplified conversions
ADTS3 ADTS2 ADTS1 ADTS0 Description
Bit 7 6543210
- - - - - - ADC9 ADC8 ADCH
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
Read/Write RRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000
Bit 7 6543210
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 - - - - - - ADCL
Read/Write RRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000
Bit 76543210
ADC7D ADC6D ADC5D ADC4D ADC3D
ACMPM
ADC2D
ACMP2D
ADC1D ADC0D DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000