Datasheet

225
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
As in Manchester mode the parity checker and generator are unavailable, the parity
should be configured to none ( write UPM1:0 to 00 in UCSRC), see Table 18-5.
• Bit 0 –Bit Order
This bit allows to change the bit ordering in the transmit and received frames.
Clear to transmit and receive LSB first (standard USART mode)
Set to transmit and receive MSB first.
19.6.5 EUSART Status Register C – EUCSRC
• Bit 7:4 –Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bits must be
written to zero when EUSCRC is written.
• Bit 3 –Frame Error Manchester
This bit is set by hardware when a framing error is detected in manchester mode. This bit is valid
when the RxC bit is set and until the receive buffer (UDR) is read.
• Bit 2 –F1617
When the receiver is configured for 16 or 17 bits in Manchester encoded mode, this bit indicates
if the received frame is 16 or 17 bits length.
Cleared: indicates that the received frame is 16 bits length.
Set: Indicates that the received frame is 17 bits length.
This bit is valid when the RxC bit is set and until the receive buffer (UDR) is read.
• Bit 1:0 –Stop bits values
When Manchester mode is activated, these bits contains the stop bits value of the previous
received frame.
When the data bits in the serial frame are standard level encoded, these bits are not updated.
Table 19-4. USART/EUSART modes selection summary
UMSEL EMCH EUSART Mode
0X0
Asynchronous up to 9 bits level encoded (standard
asynchronous USART mode)
1X0
Synchronous up to 9 bits level encoded (standard
synchronous USART mode)
0 0 1 Asynchronous up to 17 bits level encoded
0 1 1 Asynchronous up to 17 bits Manchester encoded
1 0 1 Synchronous up to 17 bits level encoded
111Reserved
Bit 76543210
----FEMF1617STP1STP0EUCSRC
Read/Write RRRRRRRR
Initial Value 00000000