Datasheet

224
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
19.6.4 EUSART Control Register B – EUCSRB
• Bit 7:5 –Reserved Bits
These bits are reserved for future use. For compatibilty with future devices, these bits must be
written to zero when EUSCRB is written.
• Bit 4 – EUSART Enable Bit
Set to enable the EUSART mode, clear to operate as standard USART.
• Bit 3– EUSBS Enable Bit
This bit selects the number of stop bits detected by the receiver.
Note: The number of stop bit inserted by the Transmitter in EUSART mode is configurable through the
USBS bit of in the of the USART.
• Bit 2–Reserved Bit
This bit is reserved for future use. For compatibility with future devices, this bit must be written to
zero when EUSCRB is written.
• Bit 1 – Manchester mode
When set the EUSART operates in manchester encoder/decoder mode (Manchester encoded
frames). When cleared the EUSART detected and transmit level encoded frames.
100114-bit
101015-bit
101116-bit
1100Reserved
1101Reserved
1110
16 OR 17 bit (for Manchester
encoded only mode)
111117-bit
Table 19-2. URxS Bits Settings
URxS3 URxS2 URxS1 URxS0 Receive Character Size
Bit 76543210
- - - EUSART EUSBS - EMCH BODR EUCSRB
Read/Write R R R R/W R/W R R/W R/W
Initial Value 00000000
Table 19-3. EUSBS Bit Settings
EUSBS Receiver Stop Bit(s)
01-bit
12-bit