Datasheet

182
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
17.2.5 SPI Status Register – SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS
is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 17-4). This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
clkio
/4
or lower.
The SPI interface on the AT90PWM2/2B/3/3B is also used for program memory and EEPROM
downloading or uploading. See Serial Programming Algorithm296 for serial programming and
verification.
Table 17-4. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
000
f
clkio
/4
001
f
clkio
/16
010f
clkio
/64
011f
clkio
/128
100f
clkio
/2
101
f
clkio
/8
110f
clkio
/32
111f
clkio
/64
Bit 76543210
SPIFWCOL–––––SPI2XSPSR
Read/Write RRRRRRRR/W
Initial Value 00000000