Datasheet

135
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Note: 1. See Figure 16-38 on page 160
Table 16-2. Block Inputs
16.4.2 Output Description
Table 16-3. Block Outputs
Table 16-4. Internal Outputs
Note: 1. See Figure 16-38 on page 160
2. See “Analog Synchronization” on page 159.
OCRnRB[15:12]
Frequency Resolution Enhancement value
(Flank Width Modulation)
Register
4 bits
CLK I/O Clock Input from I/O clock Signal
CLK PLL Clock Input from PLL Signal
SYnIn Synchronization In (from adjacent PSC)
(1)
Signal
StopIn Stop Input (for synchronized mode) Signal
Name
Description
Type
Width
PSCINn Input 0 used for Retrigger or Fault functions Signal
from A C Input 1 used for Retrigger or Fault functions Signal
Name
Description
Type
Width
Name
Description
Type
Width
PSCOUTn0 PSC n Output 0 (from part A of PSC) Signal
PSCOUTn1 PSC n Output 1 (from part B of PSC) Signal
PSCOUTn2
(PSC2 only)
PSC n Output 2 (from part A or part B of PSC) Signal
PSCOUTn3(
PSC2 only)
PSC n Output 3 (from part A or part B of PSC) Signal
Name
Description
Type
Width
SYnOut Synchronization Output
(1)
Signal
PICRn
[11:0]
PSC n Input Capture Register
Counter value at retriggering event
Register
12 bits
IRQPSCn
PSC Interrupt Request : three souces, overflow, fault, and input
capture
Signal
PSCnASY ADC Synchronization (+ Amplifier Syncho. )
(2)
Signal
StopOut Stop Output (for synchronized mode)