Features • High Performance, Low Power Atmel® AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 129 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory – 8K Bytes Flash of In-System Programmable Program Memory • Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-Sys
AT90PWM2/3/2B/3B – In-System Programmable via SPI Port – Internal Calibrated RC Oscillator ( 8 MHz) – On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz) • Operating Voltage: 2.7V - 5.5V • Extended Operating Temperature: – -40C to +105C Product Package 12 bit PWM with deadtime ADC Input ADC Diff Analog Compar Application AT90PWM2 AT90PWM2B SO24 2x2 8 1 2 One fluorescent ballast AT90PWM3 AT90PWM3B SO32, QFN32 3x2 11 2 3 HID ballast, fluorescent ballast, Motor control 1.
AT90PWM2/3/2B/3B 3. Pin Configurations Figure 3-1. SOIC 24-pin Package AT90PWM2/2B SOIC24 (PSCOUT00/XCK/SS_A) PD0 (RESET/OCD) PE0 (PSCIN0/CLKO) PD1 (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 VCC GND (MISO/PSCOUT20) PB0 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 (ADC1/RXD/DALI/ICP1A/SCK_A) PD4 Figure 3-2.
AT90PWM2/3/2B/3B Figure 3-3. QFN32 (7*7 mm) Package.
AT90PWM2/3/2B/3B 3.1 Pin Descriptions Table 3-1. Pin out description S024 Pin Number SO32 Pin Number QFN32 Pin Number Mnemonic Type 7 9 5 GND Power Ground: 0V reference 18 24 20 AGND Power Analog Ground: 0V reference for analog part 6 8 4 VCC power Power Supply: 17 23 19 AVCC Power Analog Power Supply: This is the power supply voltage for analog part Name, Function & Alternate Function For a normal use this pin must be connected.
AT90PWM2/3/2B/3B Table 3-1.
AT90PWM2/3/2B/3B Table 3-1. Pin out description (Continued) S024 Pin Number SO32 Pin Number QFN32 Pin Number Mnemonic Type 11 15 11 PE2 I/O Name, Function & Alternate Function XTAL2: XTAL OuTput ADC0 (Analog Input Channel 0) 1. PSCOUT10 & PSCOUT11 are not present on 24 pins package 4. Overview The AT90PWM2/2B/3/3B is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture.
AT90PWM2/3/2B/3B 4.1 Block Diagram Figure 4-1.
AT90PWM2/3/2B/3B The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.
AT90PWM2/3/2B/3B 4.2.5 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
AT90PWM2/3/2B/3B 5. AVR CPU Core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural Overview Figure 5-1.
AT90PWM2/3/2B/3B The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
AT90PWM2/3/2B/3B 5.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
AT90PWM2/3/2B/3B • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 5.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
AT90PWM2/3/2B/3B Figure 5-3. The X-, Y-, and Z-registers 15 XH XL 7 X-register 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.
AT90PWM2/3/2B/3B Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5-4.
AT90PWM2/3/2B/3B programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 265. 5.8.1 Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
AT90PWM2/3/2B/3B When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 5.8.
AT90PWM2/3/2B/3B 6. Memories This section describes the different memories in the AT90PWM2/2B/3/3B. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90PWM2/2B/3/3B features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 6.1 In-System Reprogrammable Flash Program Memory The AT90PWM2/2B/3/3B contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage.
AT90PWM2/3/2B/3B The AT90PWM2/2B/3/3B is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 768 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM.
AT90PWM2/3/2B/3B Figure 6-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 6.3 Next Instruction EEPROM Data Memory The AT90PWM2/2B/3/3B contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
AT90PWM2/3/2B/3B 6.3.2 The EEPROM Address Registers – EEARH and EEARL Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – – – EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bits 8..0 – EEAR8..
AT90PWM2/3/2B/3B EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 6-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.
AT90PWM2/3/2B/3B When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.
AT90PWM2/3/2B/3B Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write (unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
AT90PWM2/3/2B/3B The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
AT90PWM2/3/2B/3B 6.4 I/O Memory The I/O space definition of the AT90PWM2/2B/3/3B is shown in “Register Summary” on page 338. All AT90PWM2/2B/3/3B I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
AT90PWM2/3/2B/3B 6.5.
AT90PWM2/3/2B/3B 7. System Clock 7.1 Clock Systems and their Distribution Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 41. The clock systems are detailed below. Figure 7-1.
AT90PWM2/3/2B/3B Figure 7-2. Clock Distribution AT90PWM2B/3B PSC0/1/2 General I/O Modules CLK PLL ADC CPU Core RAM Flash and EEPROM clkADC PLL clkI/O clkCPU AVR Clock Control Unit clkFLASH Reset Logic Source Clock PLL Input Multiplexer Clock Multiplexer External Clock 7.1.1 Watchdog Timer Watchdog Clock Watchdog Oscillator (Crystal Oscillator) Calibrated RC Oscillator CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core.
AT90PWM2/3/2B/3B 7.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 7.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as illustrated Table 7-1. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 7-1.
AT90PWM2/3/2B/3B up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before starting normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 7-3. The frequency of the Watchdog Oscillator is voltage dependent as shown in “Watchdog Oscillator Frequency vs.
AT90PWM2/3/2B/3B The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-4. Table 7-4. Crystal Oscillator Operating Modes CKSEL3..1 Frequency Range(1) (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(2) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 -16.0 12 - 22 Notes: 1. The frequency ranges are preliminary values.
AT90PWM2/3/2B/3B This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 7-6. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 26-1 on page 303.
AT90PWM2/3/2B/3B Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail. The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range.
AT90PWM2/3/2B/3B Table 7-9. CKSEL 3..0 0101 Ext Osc 0001 Ext Clk Start-up Times when the PLL is selected as system clock SUT1..0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) 00 1K CK 14CK 01 1K CK 14CK + 4 ms 10 16K CK 14CK + 4 ms 11 16K CK 14CK + 64 ms 00 6 CK (1) 14CK 01 6 CK (2) 14CK + 4 ms 6 CK (3) 14CK + 64 ms 10 11 Reserved 1. This value do not provide a proper restart ; do not use PD in this clock scheme 2.
AT90PWM2/3/2B/3B Figure 7-5. PCK Clocking System AT90PWM2B/3B OSCCAL PLLF PLLE CKSEL3..0 PLOCK Lock Detector RC OSCILLATOR DIVIDE BY 8 8 MHz PLL 64x CLK PLL DIVIDE BY 2 DIVIDE BY 4 CK SOURCE XTAL1 XTAL2 7.6.2 OSCILLATORS PLL Control and Status Register – PLLCSR Bit 7 6 5 4 3 2 1 0 $29 ($29) – – – – – PLLF PLLE PLOCK Read/Write R R R R R R/W R/W R Initial Value 0 0 0 0 0 0 0/1 0 PLLCSR • Bit 7..
AT90PWM2/3/2B/3B Figure 7-6. External Clock Drive Configuration NC XTAL2 External Clock Signal XTAL1 GND Table 7-10. External Clock Frequency CKSEL3..0 Frequency Range 0000 0 - 16 MHz When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 7-11. Table 7-11. Start-up Times for the External Clock Selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14CK 01 6 CK 14CK + 4.
AT90PWM2/3/2B/3B When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency.
AT90PWM2/3/2B/3B the selcted clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 7-12.
AT90PWM2/3/2B/3B 8. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
AT90PWM2/3/2B/3B Watchdog, and the interrupt system to continue operating. This sleep mode basically halt clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts.
AT90PWM2/3/2B/3B Table 8-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Oscillator s clkADC clkPLL Main Clock Source Enabled INT3..0 PSC SPM/EEPROM Ready ADC WDT OtherI/O Idle Wake-up Sources clkIO Sleep Mode clkFLASH clkCPU Active Clock Domains X X X X X X X X X X X X X X(2) X X X X X(2) X ADC Noise Reduction Powerdown X Standby(1) X X(2) Notes: 1. Only recommended with external crystal or resonator selected as clock source. 2.
AT90PWM2/3/2B/3B • Bit 6 - PRPSC1: Power Reduction PSC1 Writing a logic one to this bit reduces the consumption of the PSC1 by stopping the clock to this module. When waking up the PSC1 again, the PSC1 should be re initialized to ensure proper operation. • Bit 5 - PRPSC0: Power Reduction PSC0 Writing a logic one to this bit reduces the consumption of the PSC0 by stopping the clock to this module. When waking up the PSC0 again, the PSC0 should be re initialized to ensure proper operation.
AT90PWM2/3/2B/3B mode. Refer to “Analog Comparator” on page 227 for details on how to configure the Analog Comparator. 8.7.3 Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
AT90PWM2/3/2B/3B 9. System Control and Reset 9.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
AT90PWM2/3/2B/3B Table 9-1. Symbol Parameter VPOT Condition Typ. Max. Units Power-on Reset Threshold Voltage (rising) 1.4 2.3 V Power-on Reset Threshold Voltage (falling)(2) 1.3 2.3 V 0.85Vcc V VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin VPOR VCC start voltage to ensure internal Power-on RESET signal VCCRR Notes: 9.0.3 Reset Characteristics(1) Min. 0.2Vcc 400 -0.05 GND ns +0.05 V VCC Rise Rate to ensure internal 0.3 V/ms Power-on RESET signal 1.
AT90PWM2/3/2B/3B Figure 9-3. MCU Start-up, RESET Extended Externally VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET 9.0.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 9-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
AT90PWM2/3/2B/3B Table 9-2. BODLEVEL Fuse Coding(1)(2) BODLEVEL 2..0 Fuses Notes: Min VBOT Typ VBOT Max VBOT Units 010 4.2 V 001 2.8 V 000 2.6 V 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.
AT90PWM2/3/2B/3B Figure 9-6. Watchdog Reset During Operation CC CK 9.0.7 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs.
AT90PWM2/3/2B/3B 1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. 4. When the DAC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC or the DAC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC or DAC is used.
AT90PWM2/3/2B/3B 9.2 Watchdog Timer AT90PWM2/2B/3/3B has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 9-7.
AT90PWM2/3/2B/3B The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
AT90PWM2/3/2B/3B The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR r16, (1<
AT90PWM2/3/2B/3B • Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF.
AT90PWM2/3/2B/3B . Table 9-6. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.
AT90PWM2/3/2B/3B 10. Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM2/2B/3/3B. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 16. 10.1 Interrupt Vectors in AT90PWM2/2B/3/3B Table 10-1. Reset and Interrupt Vectors Vector No.
AT90PWM2/3/2B/3B Table 10-1. Reset and Interrupt Vectors Vector No. Program Address 29 0x001C 30 0x001D 31 0x001E 32 0x001F Notes: Source Interrupt Definition INT3 External Interrupt Request 3 SPM READY Store Program Memory Ready 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 265. 2.
AT90PWM2/3/2B/3B 0x010 rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x011 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x012 rjmp ADC ; ADC Conversion Complete Handler 0x013 rjmp EXT_INT1 ; IRQ1 Handler 0x014 rjmp SPI_STC ; SPI Transfer Complete Handler 0x015 rjmp USART_RXC ; USART, RX Complete Handler 0x016 rjmp USART_UDRE ; USART, UDR Empty Handler 0x017 rjmp USART_TXC ; USART, TX Complete Handler 0x018 rjmp EXT_INT2 ; IRQ2 Handler 0x019 rjmp WDT ; Watchdog Timer Handler 0
AT90PWM2/3/2B/3B ; .
AT90PWM2/3/2B/3B Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
AT90PWM2/3/2B/3B 11. I/O-Ports 11.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
AT90PWM2/3/2B/3B Figure 11-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET 1 Q Pxn D 0 PORTxn Q CLR WPx DATA BUS RDx RESET WRx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clkI/O : I/O CLOCK Note: 11.2.1 WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
AT90PWM2/3/2B/3B 11.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 11.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
AT90PWM2/3/2B/3B Figure 11-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
AT90PWM2/3/2B/3B values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. TABLE 2. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16, (1<
AT90PWM2/3/2B/3B 11.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 11-5 shows how the port pin control signals from the simplified Figure 11-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 11-5.
AT90PWM2/3/2B/3B Table 11-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
AT90PWM2/3/2B/3B 11.3.1 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 SPIPS – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 63 for more details about this feature. 11.3.
AT90PWM2/3/2B/3B • ADC6/INT2 – Bit 5 ADC6, Analog to Digital Converter, input channel 6. INT2, External Interrupt source 2. This pin can serve as an External Interrupt source to the MCU. • APM0+ – Bit 4 AMP0+, Analog Differential Amplifier 0 Positive Input Channel. • AMP0- – Bit 3 AMP0-, Analog Differential Amplifier 0 Negative Input Channel. • ADC5/INT1 – Bit 2 ADC5, Analog to Digital Converter, input channel 5. INT1, External Interrupt source 1.
AT90PWM2/3/2B/3B Table 11-4 and Table 11-5 relates the alternate functions of Port B to the overriding signals shown in Figure 11-5 on page 67. Table 11-4. Overriding Signals for Alternate Functions in PB7..
AT90PWM2/3/2B/3B 11.3.3 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 11-6. Table 11-6.
AT90PWM2/3/2B/3B • PSCIN1/OC1B, Bit 1 PCSIN1, PSC 1 Digital Input. OC1B, Output Compare Match B output: This pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDC1 set “one”) to serve this function. This pin is also the output pin for the PWM mode timer function. • PSCOUT10/INT3 – Bit 0 PSCOUT10: Output 0 of PSC 1. INT3, External Interrupt source 3: This pin can serve as an external interrupt source to the MCU.
AT90PWM2/3/2B/3B Table 11-8. Overriding Signals for Alternate Functions in PC3..
AT90PWM2/3/2B/3B 11.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 11-9. Table 11-9.
AT90PWM2/3/2B/3B ACMP2, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. • ADC1/RXD/ICP1/SCK_A – Bit 4 ADC1, Analog to Digital Converter, input channel 1. RXD, USART Receive Pin. Receive Data (Data input pin for the USART). When the USART receiver is enabled this pin is configured as an input regardless of the value of DDRD4.
AT90PWM2/3/2B/3B XCK, USART External clock. The Data Direction Register (DDD0) controls whether the clock is output (DDD0 set) or input (DDD0 cleared). The XCK0 pin is active only when the USART operates in Synchronous mode. SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDD0. As a slave, the SPI is activated when this pin is driven low.
AT90PWM2/3/2B/3B Table 11-11. Overriding Signals for Alternate Functions in PD3..
AT90PWM2/3/2B/3B • XTAL1/OC0B – Bit 1 XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. OC0B, Output Compare Match B output: This pin can serve as an external output for the Timer/Counter0 Output Compare B. The pin has to be configured as an output (DDE1 set “one”) to serve this function. This pin is also the output pin for the PWM mode timer function.
AT90PWM2/3/2B/3B 11.4 11.4.1 Register Description for I/O-Ports Port B Data Register – PORTB Bit 11.4.2 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Port B Data Direction Register – DDRB Bit 11.4.
AT90PWM2/3/2B/3B 11.4.9 Port D Input Pins Address – PIND Bit 11.4.
AT90PWM2/3/2B/3B 12. External Interrupts The External Interrupts are triggered by the INT3:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0).
AT90PWM2/3/2B/3B Note: 12.0.2 1. n = 3, 2, 1 or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. External Interrupt Mask Register – EIMSK Bit 7 6 5 4 3 2 1 0 - - - - INT3 INT2 INT1 IINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bits 3..
AT90PWM2/3/2B/3B 13. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 13.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
AT90PWM2/3/2B/3B Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
AT90PWM2/3/2B/3B Table 13-1. ICPSEL1 ICPSEL1 Description 0 Select ICP1A as trigger for timer 1 input capture 1 Select ICP1B as trigger for timer 1 input capture • Bit 0 – PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.
AT90PWM2/3/2B/3B 14. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: • • • • • • • 14.
AT90PWM2/3/2B/3B The definitions in Table 14-1 are also used extensively throughout the document. Table 14-1. Definitions 14.1.2 BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register.
AT90PWM2/3/2B/3B count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
AT90PWM2/3/2B/3B Figure 14-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
AT90PWM2/3/2B/3B The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 14.
AT90PWM2/3/2B/3B non-PWM modes refer to Table 14-2 on page 98. For fast PWM mode, refer to Table 14-3 on page 98, and for phase correct PWM refer to Table 14-4 on page 98. A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits. 14.6 Modes of Operation The mode of operation, i.e.
AT90PWM2/3/2B/3B Figure 14-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
AT90PWM2/3/2B/3B inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 14-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP.
AT90PWM2/3/2B/3B 14.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5.
AT90PWM2/3/2B/3B match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ----------------N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
AT90PWM2/3/2B/3B Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) MAX - 1 TCNTn MAX BOTTOM BOTTOM + 1 TOVn Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 14-10.
AT90PWM2/3/2B/3B • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting.
AT90PWM2/3/2B/3B These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting.
AT90PWM2/3/2B/3B • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 14-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 92).
AT90PWM2/3/2B/3B changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero.
AT90PWM2/3/2B/3B The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 14.8.
AT90PWM2/3/2B/3B the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. • Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector.
AT90PWM2/3/2B/3B 15. 16-bit Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
AT90PWM2/3/2B/3B Figure 15-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB ICPSEL1 ICFn (Int.Req.) Edge Detector ICRn TCCRnA Note: 15.1.1 OCnB Noise Canceler 0 1 ICPnA ICPnB TCCRnB 1. Refer toTable 3.
AT90PWM2/3/2B/3B The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values.
AT90PWM2/3/2B/3B TABLE 3. Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included.
AT90PWM2/3/2B/3B The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. TABLE 4.
AT90PWM2/3/2B/3B The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle. TABLE 5.
AT90PWM2/3/2B/3B 15.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
AT90PWM2/3/2B/3B 15.5 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied.
AT90PWM2/3/2B/3B For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 106. 15.5.1 Input Capture Trigger Source The trigger sources for the Input Capture unit arethe Input Capture pin (ICP1A & ICP1B). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. The Input Capture pin (ICPn) IS sampled using the same technique as for the Tn pin (Figure 131 on page 84).
AT90PWM2/3/2B/3B ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “16-bit Timer/Counter1 with PWM” on page 104.
AT90PWM2/3/2B/3B updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 106. 15.6.
AT90PWM2/3/2B/3B Figure 15-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
AT90PWM2/3/2B/3B while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page 114.) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 123. 15.8.1 Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0).
AT90PWM2/3/2B/3B An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
AT90PWM2/3/2B/3B Figure 15-7. Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value.
AT90PWM2/3/2B/3B The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ---------------------------------N 1 + TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle.
AT90PWM2/3/2B/3B Figure 15-8. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM.
AT90PWM2/3/2B/3B the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
AT90PWM2/3/2B/3B Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
AT90PWM2/3/2B/3B The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 15.
AT90PWM2/3/2B/3B Figure 15-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx New OCRnx Value Old OCRnx Value (Update at TOP) Figure 15-13 shows the same timing data, but with the prescaler enabled. Figure 15-13.
AT90PWM2/3/2B/3B I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA or OCnB pin must be set in order to enable the output driver. When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 15-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). Table 15-2.
AT90PWM2/3/2B/3B Table 15-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COMnA1/COMnB1 COMnA0/COMnB0 0 1 WGMn3:0 = 8, 9 10 or 11: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OCnA/OCnB on Compare Match when upcounting. Set OCnA/OCnB on Compare Match when downcounting. Set OCnA/OCnB on Compare Match when upcounting.
AT90PWM2/3/2B/3B Note: 15.10.2 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.
AT90PWM2/3/2B/3B If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 15.10.
AT90PWM2/3/2B/3B OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnx pin. The Output Compare Registers are 16-bit in size.
AT90PWM2/3/2B/3B Interrupt Vector (see “Reset and Interrupt Vectors Placement in AT90PWM2/2B/3/3B(1)” on page 58) is executed when the OCF1A Flag, located in TIFR1, is set. • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled.
AT90PWM2/3/2B/3B 16. Power Stage Controller – (PSC0, PSC1 & PSC2) The Power Stage Controller is a high performance waveform controller. 16.1 Features • • • • • • • • • • • • 16.2 PWM waveform generation function (2 complementary programmable outputs) Dead time control Standard mode up to 12 bit resolution Frequency Resolution Enhancement Mode (12 + 4 bits) Frequency up to 64 Mhz Conditional Waveform on External Events (Zero Crossing, Current Sensing ...
AT90PWM2/3/2B/3B 16.3 PSC Description Figure 16-1.
AT90PWM2/3/2B/3B 16.3.1 PSC2 Distinctive Feature Figure 16-2.
AT90PWM2/3/2B/3B 16.4 Signal Description Figure 16-3. PSC External Block View CLK PLL CLK I/O SYnIn StopOut OCRnRB[11:0] OCRnSB[11:0] OCRnRA[11:0] OCRnSA[11:0] OCRnRB[15:12] (Flank Width Modulation) PICRn[11:0] 12 PSCOUTn0 12 PSCOUTn1 12 (1) PSCOUTn2 12 (1) PSCOUTn3 4 12 PSCINn IRQ PSCn Analog Comparator n Output StopIn SYnOut PSCnASY Note: 1. available only for PSC2 2. n = 0, 1 or 2 16.4.1 Input Description Table 16-1.
AT90PWM2/3/2B/3B OCRnRB[15:12] Frequency Resolution Enhancement value (Flank Width Modulation) Register 4 bits CLK I/O Clock Input from I/O clock Signal CLK PLL Clock Input from PLL SYnIn Synchronization In (from adjacent PSC) StopIn Stop Input (for synchronized mode) Note: Signal (1) Signal Signal 1. See Figure 16-38 on page 160 Table 16-2. Name 16.4.
AT90PWM2/3/2B/3B 16.5 16.5.1 Functional Description Waveform Cycles The waveform generated by PSC can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform is sub-cycle A in the following figure. The second waveform is relative to PSCOUTn1 output and part B of PSC. The part of this waveform is sub-cycle B in the following figure. The complete waveform is ended with the end of sub-cycle B.
AT90PWM2/3/2B/3B 16.5.2 Running Mode Description Waveforms and length of output signals are determined by Time Parameters (DT0, OT0, DT1, OT1) and by the running mode. Four modes are possible : 16.5.2.1 – Four Ramp mode – Two Ramp mode – One Ramp mode – Center Aligned mode Four Ramp Mode In Four Ramp mode, each time in a cycle has its own definition Figure 16-6.
AT90PWM2/3/2B/3B Figure 16-7. PSCn0 & PSCn1 Basic Waveforms in Two Ramp mode OCRnRA PSC Counter OCRnSA OCRnRB OCRnSB 0 0 On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time 1 Dead-Time 0 PSC Cycle PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH/L + 1) * 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L + 1) * 1/Fclkpsc Note: 16.5.2.
AT90PWM2/3/2B/3B Figure 16-8. PSCn0 & PSCn1 Basic Waveforms in One Ramp mode OCRnRB OCRnSB OCRnRA PSC Counter OCRnSA 0 On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time 1 Dead-Time 0 PSC Cycle On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH/L + 1) * 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) * 1/Fclkpsc Note: 16.5.2.
AT90PWM2/3/2B/3B Figure 16-9.
AT90PWM2/3/2B/3B 16.5.3 Fifty Percent Waveform Configuration When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRnSBH/L and OCRnRBH/L registers in OCRnSAH/L and OCRnRAH/L registers. So it is not necessary to program OCRnSAH/L and OCRnRAH/L registers. 16.
AT90PWM2/3/2B/3B fractional divider number. The resulting output frequency is the average of the frequencies in the frame. The fractional divider (d) is given by OCRnRB[15:12]. The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0) and PSCOUTn1 On Time + DeadTime (OT1+DT1) values. These values are 12 bits numbers. The frequency adjustment can only be done in steps like the dedicated counters.
AT90PWM2/3/2B/3B 16.7.1 Frequency distribution The frequency modulation is done by switching two frequencies in a 16 consecutive cycle frame. These two frequencies are fb1 and fb2 where fb1 is the nearest base frequency above the wanted frequency and fb2 is the nearest base frequency below the wanted frequency. The number of fb1 in the frame is (d-16) and the number of fb2 is d. The fb1 and fb2 frequencies are evenly distributed in the frame according to a predefined pattern.
AT90PWM2/3/2B/3B 16.7.2 16.7.2.1 Modes of Operation Normal Mode The simplest mode of operation is the normal mode. See Figure 16-6. The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given by the OT1 value. Both of them are 12 bit values. Thanks to DT0 & DT1 to adjust the dead time between PSCOUTn0 and PSCOUTn1 active signals.
AT90PWM2/3/2B/3B 16.8 PSC Inputs Each part A or B of PSC has its own system to take into account one PSC input. According to PSC n Input A/B Control Register (see description in “PSC n Input A Control Register – PFRCnA” on page 169page 169), PSCnIN0/1 input can act has a Retrigger or Fault input. This system A or B is also configured by this PSC n Input A/B Control Register (PFRCnA/B). Figure 16-14.
AT90PWM2/3/2B/3B Figure 16-15. PSCOUTn0 retriggered by PSCn Input A (Edge Retriggering) On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input A (falling edge) PSCn Input A (rising edge) Dead-Time 0 Note: Dead-Time 1 This exemple is given in “Input Mode 8” in “2 or 4 ramp mode” See Figure 16-31. for details. Figure 16-16. PSCOUTn0 retriggered by PSCn Input A (Level Acting) On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) Dead-Time 0 Note: 16.8.
AT90PWM2/3/2B/3B Figure 16-17. PSCOUTn1 retriggered by PSCn Input B (Edge Retriggering) On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input B (falling edge) PSCn Input B (rising edge) Dead-Time 0 Note: Dead-Time 1 Dead-Time 0 This exemple is given in “Input Mode 8” in “2 or 4 ramp mode” See Figure 16-31. for details. Figure 16-18. PSCOUTn1 retriggered by PSCn Input B (Level Acting) On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 PSCn Input B (high level) PSCn Input B (low level) Dead-Time 0 Note: 16.8.
AT90PWM2/3/2B/3B Figure 16-19. Burst Generation OFF BURST PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) 16.8.4 PSC Input Configuration The PSC Input Configuration is done by programming bits in configuration registers. 16.8.4.1 Filter Enable If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal.
AT90PWM2/3/2B/3B If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low - In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and OnTime0 period (respectively Dead-Time1 and On-Time1 for PSCn Input B). - In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp. 16.8.4.
AT90PWM2/3/2B/3B 16.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait Figure 16-20. PSCn behaviour versus PSCn Input A in Fault Mode 1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSC Input A event occurs, PSC releases PSCOUTn0, waits for PSC Input A inactive state and then jumps and executes DT1 plus OT1. Figure 16-21.
AT90PWM2/3/2B/3B 16.10 PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait Figure 16-22. PSCn behaviour versus PSCn Input A in Fault Mode 2 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCn Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1 and then waits for PSC Input A inactive state.
AT90PWM2/3/2B/3B 16.11 PSC Input Mode 3: Stop signal, Execute Opposite while Fault active Figure 16-24. PSCn behaviour versus PSCn Input A in Mode 3 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT1 OT1 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSC Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1 plus DT0 while PSC Input A is in active state.
AT90PWM2/3/2B/3B Figure 16-26. PSC behaviour versus PSCn Input A or Input B in Mode 4 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Figure 16-27. PSC behaviour versus PSCn Input A or Input B in Fault Mode 4 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on OnTime1/Dead-Time1. 16.
AT90PWM2/3/2B/3B 16.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. Figure 16-29. PSC behaviour versus PSCn Input A in Fault Mode 6 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Used in Fault mode 6, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 16.15 PSC Input Mode 7: Halt PSC and Wait for Software Action Figure 16-30.
AT90PWM2/3/2B/3B Figure 16-31. PSC behaviour versus PSCn Input A in Mode 8 DT0 OT0 DT1 DT0 OT0 OT1 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is modulated by the occurence of significative edge of retriggering input. Figure 16-32.
AT90PWM2/3/2B/3B Figure 16-33. PSC behaviour versus PSCn Input A in Mode 9 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurence of significative edge of retriggering input. Only the output is disactivated when significative edge on retriggering input occurs. Note: In this mode the output of the PSC becomes active during the next ramp even if the Retrigger/Fault input is actve.
AT90PWM2/3/2B/3B Figure 16-35. PSC behaviour versus PSCn Input A in Mode 14 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurence of significative edge of retriggering input. Figure 16-36.
AT90PWM2/3/2B/3B 16.18.1 Available Input Mode according to Running Mode Some Input Modes are not consistent with some Running Modes. So the table below gives the input modes which are valid according to running modes.. Table 16-7.
AT90PWM2/3/2B/3B 16.19 PSC2 Outputs 16.19.1 Output Matrix PSC2 has an output matrix which allow in 4 ramp mode to program a value of PSCOUT20 and PSCOUT21 binary value for each ramp. Table 16-8. Output Matrix versus ramp number Ramp 0 Ramp 1 Ramp 2 Ramp 3 PSCOUT20 POMV2A0 POMV2A1 POMV2A2 POMV2A3 PSCOUT21 POMV2B0 POMV2B1 POMV2B2 POMV2B3 PSCOUT2m takes the value given in Table 16-8. during all corresponding ramp.
AT90PWM2/3/2B/3B This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs. In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchronization of the ADC. It this case, it’s minimum value is 1. 16.21 Interrupt Handling As each PSC can be dedicated for one function, each PSC has its own interrupt system (vector ...
AT90PWM2/3/2B/3B Thanks to this feature, we can for example configure two PSC in slave mode (PARUNn = 1 / PRUNn = 0) and one PSC in master mode (PARUNm = 0 / PRUNm = 0). This PSC master can start all PSC at the same moment (PRUNm = 1). 16.22.1 Fault events in Autorun mode To complete this master/slave mechanism, fault event (input mode 7) is propagated from PSCn1 to PSCn and from PSCn to PSCn-1. A PSC which propagate a Run signal to the following PSC stops this PSC when the Run signal is deactivate.
AT90PWM2/3/2B/3B Table 16-9. Output Clock versus Selection and Prescaler PCLKSELn PPREn1 PPREn0 CLKPSCn output AT90PWM2/3 CLKPSCn output AT90PWM2B/3B 0 0 0 CLK I/O CLK I/O 0 0 1 CLK I/O / 4 CLK I/O / 4 0 1 0 CLK I/O / 16 CLK I/O / 32 0 1 1 CLK I/O / 64 CLK I/O / 256 1 0 0 CLK PLL CLK PLL 1 0 1 CLK PLL / 4 CLK PLL / 4 1 1 0 CLK PLL / 16 CLK PLL / 32 1 1 1 CLK PLL / 64 CLK PLL / 256 16.
AT90PWM2/3/2B/3B 16.25 PSC Register Definition Registers are explained for PSC0. They are identical for PSC1. For PSC2 only different registers are described. 16.25.1 PSC 0 Synchro and Output Configuration – PSOC0 Bit 16.25.2 7 6 5 4 3 2 1 0 - - PSYNC01 PSYNC00 - POEN0B - POEN0A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PSC 1 Synchro and Output Configuration – PSOC1 Bit 16.25.
AT90PWM2/3/2B/3B Table 16-12. Synchronization Source Description in Centered Mode PSYNCn1 PSYNCn0 Description 0 0 Send signal on match with OCRnRA (during counting down of PSC). The min value of OCRnRA must be 1. 0 1 Send signal on match with OCRnRA (during counting up of PSC). The min value of OCRnRA must be 1.
AT90PWM2/3/2B/3B 16.25.6 Output Compare SB Register – OCRnSBH and OCRnSBL Bit 7 6 5 4 – – – – 3 2 1 0 OCRnSB[11:8] OCRnSBH OCRnSB[7:0] 16.25.
AT90PWM2/3/2B/3B • Bit 6 - PALOCKn: PSC n Autolock When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The update of the PSC internal registers will be done at the end of the PSC cycle if the Output Compare Register RB has been the last written.
AT90PWM2/3/2B/3B • Bit 7:6 – PPRE01:0 : PSC 0 Prescaler Select This two bits select the PSC input clock division factor. All generated waveform will be modified by this factor. Table 16-14.
AT90PWM2/3/2B/3B • Bit 7:6 – PPRE11:0 : PSC 1 Prescaler Select This two bits select the PSC input clock division factor.All generated waveform will be modified by this factor. Table 16-15.
AT90PWM2/3/2B/3B • Bit 7:6 – PPRE21:0 : PSC 2 Prescaler Select This two bits select the PSC input clock division factor.All generated waveform will be modified by this factor. Table 16-16.
AT90PWM2/3/2B/3B 16.25.15 PSC n Input B Control Register – PFRCnB Bit 7 6 5 4 PCAEnB PISELnB PELEVnB PFLTEnB 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0 PFRCnB The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The 2 blocks are identical, so they are configured on the same way.
AT90PWM2/3/2B/3B PRFMnx3:0 Description 1001b PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 1010b Reserved (do not use) 1011b 1100b 1101b 1110b 1111b PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output Reserved (do not use) 16.25.16 PSC 0 Input Capture Register – PICR0H and PICR0L Bit 7 6 5 4 PCST0 – – – 3 2 1 0 PICR0[11:8] PICR0H PICR0[7:0] PICR0L Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 16.25.
AT90PWM2/3/2B/3B 16.26 PSC2 Specific Register 16.26.
AT90PWM2/3/2B/3B 16.26.4 PSC2 Interrupt Mask Register – PIM2 Bit 7 6 5 4 3 2 1 0 - - PSEIE2 PEVE2B PEVE2A - - PEOPE2 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 PIM2 • Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable When this bit is set, the PSEIn bit (if set) generate an interrupt.
AT90PWM2/3/2B/3B This feature is useful to detect that a PSC output doesn’t change due to a frozen external input signal. • Bit 5 – PSEIn : PSC n Synchro Error Interrupt This bit is set by hardware when the update (or end of PSC cycle) of the PSCn configured in auto run (PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated the input run signal. (For PSC0, PSCn-1 is PSC2). Must be cleared by software by writing a one to its location.
AT90PWM2/3/2B/3B 17. Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM2/2B/3/3B and peripheral devices or between several AVR devices. The AT90PWM2/2B/3/3B SPI includes the following features: 17.
AT90PWM2/3/2B/3B the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start.
AT90PWM2/3/2B/3B Table 17-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input Note: SS User Defined Input 1. See “Alternate Functions of Port B” on page 69 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
AT90PWM2/3/2B/3B TABLE 2.
AT90PWM2/3/2B/3B TABLE 2.
AT90PWM2/3/2B/3B means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 17.2.
AT90PWM2/3/2B/3B 17.2.4 SPI Control Register – SPCR Bit 7 6 5 4 3 2 1 0 SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. • Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled.
AT90PWM2/3/2B/3B Table 17-4. 17.2.
AT90PWM2/3/2B/3B 17.2.6 SPI Data Register – SPDR Bit 7 6 5 4 3 2 1 0 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined • Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission.
AT90PWM2/3/2B/3B Figure 17-4.
AT90PWM2/3/2B/3B 18. USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: 18.1 Features • • • • • • • • • • • • • 18.
AT90PWM2/3/2B/3B Figure 18-1. USART Block Diagram(1) Clock Generator UBRR[H:L] CLKio BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver RECEIVE SHIFT REGISTER UDR UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL DATA RECOVERY PIN CONTROL RxD PARITY CHECKER (Receive) UCSRB UCSRC 1. Refer to Pin Configurations3, Table 11-9 on page 75, and Table 11-7 on page 73 for USART pin placement.
AT90PWM2/3/2B/3B chronous, Master synchronous and Slave synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode).
AT90PWM2/3/2B/3B Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. Table 18-1.
AT90PWM2/3/2B/3B Note that fclkio depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 18.3.4 Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same.
AT90PWM2/3/2B/3B Figure 18-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting.
AT90PWM2/3/2B/3B that there are no unread data in the receive buffer. Note that the TXC flag must be cleared before each transmission (before UDR is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.
AT90PWM2/3/2B/3B chronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock. 18.6.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.
AT90PWM2/3/2B/3B TABLE 4.
AT90PWM2/3/2B/3B global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
AT90PWM2/3/2B/3B TABLE 3. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer lds r16, UDR ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRA & (1<
AT90PWM2/3/2B/3B TABLE 2.
AT90PWM2/3/2B/3B The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 18.7.3 Receive Complete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer.
AT90PWM2/3/2B/3B Figure 18-5. Data OverRun example RxD CH1 CH2 CH3 DOR RxC t Software Access to Receive buffer RxC=1 UDR=CH1 DOR=0 RxC=1 UDR=CH2 DOR=0 RxC=1 UDR=XX DOR=1 The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA.
AT90PWM2/3/2B/3B TABLE 2. Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC0 ret lds r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1<
AT90PWM2/3/2B/3B figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit. 18.8.
AT90PWM2/3/2B/3B 18.8.3 Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see Table 18-2) base frequency, the Receiver will not be able to synchronize the frames to the start bit.
AT90PWM2/3/2B/3B Table 18-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 94.12 105.66 +5.66/-5.88 ± 2.5 6 94.92 104.92 +4.92/-5.08 ± 2.0 7 95.52 104,35 +4.35/-4.48 ± 1.5 8 96.00 103.90 +3.90/-4.00 ± 1.5 9 96.39 103.53 +3.53/-3.61 ± 1.5 10 96.70 103.23 +3.23/-3.30 ± 1.
AT90PWM2/3/2B/3B (TXBn = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character frame format. The following procedure should be used to exchange data in Multi-processor Communication mode: 1. All Slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set). 2. The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the RXC flag in UCSRA will be set as normal. 3.
AT90PWM2/3/2B/3B 18.10.2 USART Control and Status Register A – UCSRA Bit Read/Write Initial Value 0 7 6 5 4 3 2 1 0 RXC TXC UDRE FE DOR UPE U2X MPCM R R/W R R R R R/W R/W 0 1 0 0 0 0 UCSRA 0 • Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data).
AT90PWM2/3/2B/3B • Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. This bit is available in both USART and EUSART modes. • Bit 0 – MPCM: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode.
AT90PWM2/3/2B/3B when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxDn port. This bit is available for both USART and EUSART mode. • Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. This bit have no effect when the EUSART mode is enabled.
AT90PWM2/3/2B/3B Table 18-5. UPM Bits Settings UPM1 UPM0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity This setting is available in EUSART mode only when data bits are level encoded (in Manchester the parity checker and generator are not available). • Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting.
AT90PWM2/3/2B/3B Table 18-8. Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxD Pin) 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge UCPOL 18.10.
AT90PWM2/3/2B/3B Table 18-9. Examples of UBRR Settings for Commonly Frequencies fclkio = 1.0000 MHz fclkio = 1.8432 MHz fclkio = 2.0000 MHz Baud Rate (bps) UBRR 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.
AT90PWM2/3/2B/3B Table 18-10. Examples of UBRR Settings for Commonly Frequencies (Continued) fclkio = 3.6864 MHz Baud Rate (bps) U2X = 0 UBRR fclkio = 4.0000 MHz U2X = 1 Error UBRR U2X = 0 Error UBRR fclkio = 7.3728 MHz U2X = 1 Error UBRR U2X = 0 Error UBRR U2X = 1 Error UBRR Error 500k – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8% 1M – – – – – – – – – – 0 -7.8% Max. (1) 230.4 kbps 1. 460.8 kbps 250 kbps 0.5 Mbps 460.8 kpbs 921.6 kbps UBRR = 0, Error = 0.
AT90PWM2/3/2B/3B Table 18-12. Examples of UBRR Settings for Commonly Frequencies (Continued) fclkio = 12.0000 MHz fclkio = 14.7456 MHz fclkio = 16.0000 MHz Baud Rate (bps) UBRR 2400 312 -0.2% 624 0.0% 383 0.0% 767 0.0% 416 -0.1% 832 0.0% 4800 155 0.2% 312 -0.2% 191 0.0% 383 0.0% 207 0.2% 416 -0.1% 9600 77 0.2% 155 0.2% 95 0.0% 191 0.0% 103 0.2% 207 0.2% 14.4k 51 0.2% 103 0.2% 63 0.0% 127 0.0% 68 0.6% 138 -0.1% 19.2k 38 0.2% 77 0.2% 47 0.
AT90PWM2/3/2B/3B 19. EUSART (Extended USART) The Extended Universal Synchronous and Asynchronous serial Receiver and Transmitter (EUSART) provides functionnal extensions to the USART. 19.1 Features • • • • • 19.
AT90PWM2/3/2B/3B The EUSART supports more serial frame formats than the standard USART interface: • Asynchonous frames • – Standard bit level encoded – Manchester bit encoded Synchronous frames – 19.3 In this mode only the Standard bit level encoded is available Serial Frames A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. 19.3.
AT90PWM2/3/2B/3B 19.3.3 Manchester encoding Manchester encoding (also know as Biphase Code) is a synchronous clock encoding technique used to encode the clock and data of a synchronous bit stream. In this technique, the actual binary data to be transmitted are not sent as a sequence of logic 1's and 0's as in level encoded way as in standard USART (known technically as Non Return to Zero (NRZ)).
AT90PWM2/3/2B/3B 19.3.3.2 Manchester decoder When configured in Manchester mode, the EUSART receiver is able to receive serial frame using a 17-bit shift register, an edge detector and several data/control registers. The Manchester decoder receives a frame from the RxD pin of the EUSART interface and loads the received data in the EUSART data register (UDR and EUDR). The bit order of the data bits in the frame is configurable to handle MSB or LSB first.
AT90PWM2/3/2B/3B Figure 19-4. Manchester Decoder operation Data Clock Start Bit Bit 3 Bit 2 Bit 1 Delayed edge Manchester Data N4 N1/2 Manchester Decoder Counter N3 N2 N1 N2/4 N2/2 N3/4 N3/2 N4/4 Detection Window Internal Manchester Clock Decoded Data Note: 19.3.4.
AT90PWM2/3/2B/3B Figure 19-5.
AT90PWM2/3/2B/3B 19.4 19.4.1 Configuring the EUSART Data Transmission – EUSART Transmitter The EUSART Transmitter is enabled in the same way as standard USART, by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden by the EUSART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
AT90PWM2/3/2B/3B 19.4.4 Sending 17 Data Bit Frames In this configuration the seventeenth bit shoud be loaded in the RXB8 bit register, the rest of the most significant bits (9, 10, 11, 12, 13, 14, 15 and 16) should be loaded in the EUDR register, before the low byte of the character is written to UDR. 19.4.5 Transmitter Flags and Interrupts The behavior of the EUSART is the same as in USART mode (See “Receive Complete Flag and Interrupt”).
AT90PWM2/3/2B/3B The following code example shows a simple EUSART receive function. TABLE 3.
AT90PWM2/3/2B/3B All the receiver error flags are valid only when the RxC bit is set and until the UDR register is read. 19.5.5.1 Parity Checker The parity checker of the EUSART is available only when data bits are level encoded and behaves as is USART mode (See Parity checker of the USART). 19.5.5.2 OverRun The Data OverRun (DOR bit of USCRA) flag indicates data loss due to a receiver buffer full condition. This flag operates as in USART mode (See USART section). 19.6 EUSART Registers Description 19.
AT90PWM2/3/2B/3B Figure 19-6. 9 bits communication data access Data 8:0 8 7 EUDR 19.6.2.3 0 UDR UDR/EUDR data access from 13 to 17 bits per character When the EUSART is used in 13, 14, 15, 16 or 17 bits per character mode, the EUDR/UDR registers are used in combinaison with the RxB8/TxB8 bit for data access. For 13, 14, 15 or 16 bit character the upper unused bits in EUDR will be ignored by the Transmitter and set to zero by the Receiver. In transmitter mode, the data should be written MSB first.
AT90PWM2/3/2B/3B 19.6.3 EUSART Control and Status Register A – EUCSRA Bit 7 6 5 4 3 2 1 0 UTxS3 UTxS2 UTxS1 UTxS0 URxS3 URxS2 URxS1 URxS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 1 1 0 0 1 1 EUCSRA • Bit 7:4 – EUSART Transmit Character Size The UTxS3:0 bits sets the number of data bits (Character Size) in a frame the Transmitter use. Table 19-1.
AT90PWM2/3/2B/3B Table 19-2. 19.6.
AT90PWM2/3/2B/3B Table 19-4.
AT90PWM2/3/2B/3B 19.6.6 Manchester receiver Baud Rate Registers – MUBRRL and MUBRRH Bit 15 14 13 12 11 10 9 8 MUBRR[15:8] MUBRRH MUBRR[7:0] 7 Read/Write Initial Value 6 5 4 3 MUBRRL 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • Bit 15:0 – MUBRR15:0: Manchester Receiver Baud Rate Register This is a 16-bit register which contains the maximum value for the Machester receiver counter.
AT90PWM2/3/2B/3B 20. Analog Comparator The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM. 20.1 Overview The AT90PWM2/2B/3/3B features three fast analog comparators. Each comparator has a dedicated input on the positive input, and the negative input can be configured as: • a steady value among the 4 internal reference levels defined by the Vref selected thanks to the REFS1:0 bits in ADMUX register.
AT90PWM2/3/2B/3B Figure 20-1.
AT90PWM2/3/2B/3B • Bit 5, 4– AC0IS1, AC0IS0: Analog Comparator 0 Interrupt Select bit These 2 bits determine the sensitivity of the interrupt trigger. The different setting are shown in Table 20-1. Table 20-1.
AT90PWM2/3/2B/3B Table 20-3. Interrupt sensitivity selection AC1IS1 AC1IS0 Description 0 0 Comparator Interrupt on output toggle 0 1 Reserved 1 0 Comparator interrupt on output falling edge 1 1 Comparator interrupt on output rising edge • Bit 3– AC1ICE: Analog Comparator 1 Interrupt Capture Enable bit Set this bit to enable the input capture of the Timer/Counter1 on the analog comparator event.
AT90PWM2/3/2B/3B • Bit 6– AC2IE: Analog Comparator 2 Interrupt Enable bit Set this bit to enable the analog comparator 2 interrupt. Clear this bit to disable the analog comparator 2 interrupt. • Bit 5, 4– AC2IS1, AC2IS0: Analog Comparator 2 Interrupt Select bit These 2 bits determine the sensitivity of the interrupt trigger. The different setting are shown in Table 20-1. Table 20-5.
AT90PWM2/3/2B/3B AC2IE in AC2CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions. • Bit 5– AC1IF: Analog Comparator 1 Interrupt Flag Bit This bit is set by hardware when comparator 1 output event triggers off the interrupt mode defined by AC1IS1 and AC1IS0 bits in AC1CON register. This bit is cleared by hardware when the corresponding interrupt vector is executed in case the AC1IE in AC1CON register is set.
AT90PWM2/3/2B/3B analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
AT90PWM2/3/2B/3B 21. Analog to Digital Converter - ADC 21.1 Features • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 8- 320 µs Conversion Time Up to 125 kSPS at Maximum Resolution 11 Multiplexed Single Ended Input Channels Two Differential input channels with accurate programmable gain 5, 10, 20 and 40 Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
AT90PWM2/3/2B/3B Figure 21-1. Analog to Digital Converter Block Schematic AREF AVCC Internal 2.
AT90PWM2/3/2B/3B 21.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
AT90PWM2/3/2B/3B Figure 21-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START CLKADC ADATE ADIF SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
AT90PWM2/3/2B/3B When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Changing Channel or Reference Selection” on page 239 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 3.
AT90PWM2/3/2B/3B Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 13 14 15 16 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Conversion Complete Prescaler Reset MUX and REFS Update Figure 21-7.
AT90PWM2/3/2B/3B If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings.
AT90PWM2/3/2B/3B If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 26-5 on page 307. 21.6 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure that the ADATE bit is reset. b.
AT90PWM2/3/2B/3B Figure 21-8. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 21.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible.
AT90PWM2/3/2B/3B 21.6.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by shortening both differential inputs using the AMPxIS bit with both inputs unconnected. (See “Amplifier 0 Control and Status register – AMP0CSR” on page 256. and See “Amplifier 1Control and Status register – AMP1CSR” on page 257.).
AT90PWM2/3/2B/3B Figure 21-11. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 21-12.
AT90PWM2/3/2B/3B Figure 21-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 21.7 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
AT90PWM2/3/2B/3B Figure 21-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF /Gain 0x3FF 0 VREF/Gain Differential Input Voltage (Volts) 0x200 Table 21-2. Correlation Between Input Voltage and Output Codes VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 0.999 VREF /GAIN 0x1FF 511 VADCm + 0.998 VREF /GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF /GAIN 0x3FF -1 ... ... ...
AT90PWM2/3/2B/3B – ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. Example 2: 21.8 – ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, left adjusted result) – Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. – ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029. – ADCL will thus read 0x40, and ADCH will read 0x0A. Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.
AT90PWM2/3/2B/3B • Bit 3, 2, 1, 0 – MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits These 4 bits determine which analog inputs are connected to the ADC input. The different setting are shown in Table 21-4. Table 21-4.
AT90PWM2/3/2B/3B In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register. See Table 21-6 on page 250. • Bit 4– ADIF: ADC Interrupt Flag Set by hardware as soon as a conversion is complete and the Data register are updated with the conversion result. Cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF can be cleared by writing it to logical one.
AT90PWM2/3/2B/3B In accordance with the Table 21-6, these 3 bits select the interrupt event which will generate the trigger of the start of conversion. The start of conversion will be generated by the rising edge of the selected interrupt flag whether the interrupt is enabled or not. In case of trig on PSCnASY event, there is no flag. So in this case a conversion will start each time the trig event appears and the previous conversion is completed Table 21-6.
AT90PWM2/3/2B/3B Table 21-7. ADTS3 ADTS2 ADTS1 ADTS0 Description 1 0 1 0 PSC2ASY Event(1) 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved 1. 21.8.4 ADC Auto Trigger Source Selection for amplified conversions For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock source.
AT90PWM2/3/2B/3B • Bit 7:0 – ADC7D..ADC0D: ACMP2:1 and ADC7:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 21.8.
AT90PWM2/3/2B/3B - By setting the ADASCR (Analog to Digital Conversion on Amplified Channel Start Conversion Request) bit in the ADCSRB register on AT90PWM2/3. Then, the ADSC bit of the ADCSRA Register is automatically set on the next amplifier clock event, and a conversion is started. - By setting the ADSC (ADC Start conversion) bit in the ADCSRB register on AT90PWM2B/3B. Until the conversion is not achieved, it is not possible to start a conversion on another channel.
AT90PWM2/3/2B/3B AT90PWM2B/3B: On PWM2B/3B, the amplifier has been improved in order to speed-up the conversion time.The proposed improvement takes advantage of the amplifier characteristics to ensure a conversion in less time. In order to have a better understanding of the functioning of the amplifier synchronization, a timing diagram example is shown Figure for AT90PWM2B/3B. As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion is started.
AT90PWM2/3/2B/3B Signal to be measured PSC Block PSCn_ASY AMPLI_clk (Sync Clock) CK ADC Valid sample ADSC ADC ADC Activity ADC Conv ADC Sampling ADC Sampling Aborted ADC Conv ADC Sampling ADCResult Ready ADCResult Ready 255 4317K–AVR–03/2013
AT90PWM2/3/2B/3B The block diagram of the two amplifiers is shown on Figure 21-18. Figure 21-18. Amplifiers block diagram + SAMPLING AMP0+ AMP0- Toward ADC MUX (AMP0) ADCK/8 ASY0 ASY1 ASY2 00 01 10 01 Sampling Clock AMP0EN AMP0IS AMP0G1 AMP0G0 - - AMP0TS1AMP0TS0 AMP0CSR + SAMPLING AMP1+ AMP1- Toward ADC MU (AMP1) ADCK/8 ASY0 ASY1 ASY2 00 01 10 01 Sampling Clock AMP1EN AMP1IS AMP1G1 AMP1G0 - AMP1TS1AMP1TS0 - AMP1CSR 21.
AT90PWM2/3/2B/3B • Bit 7 – AMP0EN: Amplifier 0 Enable Bit Set this bit to enable the Amplifier 0. Clear this bit to disable the Amplifier 0. Clearing this bit while a conversion is running will take effect at the end of the conversion. Warning: Always clear AMP0TS1:0 when clearing AMP0EN. • Bit 6– AMP0IS: Amplifier 0 Input Shunt Set this bit to short-circuit the Amplifier 0 input. Clear this bit to normally use the Amplifier 0.
AT90PWM2/3/2B/3B • Bit 6– AMP1IS: Amplifier 1 Input Shunt Set this bit to short-circuit the Amplifier 1 input. Clear this bit to normally use the Amplifier 1. • Bit 5, 4– AMP1G1, 0: Amplifier 1 Gain Selection Bits These 2 bits determine the gain of the amplifier 0. The different setting are shown in Table 21-10. Table 21-10.
AT90PWM2/3/2B/3B 22. Digital to Analog Converter - DAC 22.1 Features • • • • • 10 bits resolution 8 bits linearity +/- 0.5 LSB accuracy between 150mV and AVcc-150mV Vout = DAC*Vref/1023 The DAC could be connected to the negative inputs of the analog comparators and/or to a dedicated output driver. • Output impedance around 100 Ohm. The AT90PWM2/2B/3/3B features a 10-bit Digital to Analog Converter.
AT90PWM2/3/2B/3B Figure 22-1. Digital to Analog Converter Block Schematic DAC Result D2A pin VRef DAC Output Driver 10 1 0 10 10 DAC High bits DAC Low bits Sources DACH Update DAC Trigger Edge Detector DAATE DACL DATS2 DATS1 DATS0 - DALA DAOE DAEN DACON 22.2 Operation The Digital to Analog Converter generates an analog signal proportional to the value of the DAC registers value.
AT90PWM2/3/2B/3B rupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 22.3.1 DAC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the DAC. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the DAC through a passive switch. The internal 2.
AT90PWM2/3/2B/3B Table 22-1. DAC Auto Trigger source selection (Continued) DATS2 DATS1 DATS0 Description 1 0 0 Timer/Counter0 Overflow 1 0 1 Timer/Counter1 Compare Match B 1 1 0 Timer/Counter1 Overflow 1 1 1 Timer/Counter1 Capture Event • Bit 2 – DALA: Digital to Analog Left Adjust Set this bit to left adjust the DAC input data. Clear it to right adjust the DAC input data. The DALA bit affects the configuration of the DAC data registers.
AT90PWM2/3/2B/3B To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediate value, the DAC input values which are really converted into analog signal are buffering into unreachable registers. In normal mode, the update of the shadow register is done when the register DACH is written. In case DAATE bit is set, the DAC input values will be updated on the trigger event selected through DATS bits.
AT90PWM2/3/2B/3B 23. debugWIRE On-chip Debug System 23.1 Features • • • • • • • • • • 23.
AT90PWM2/3/2B/3B 23.4 • Pull-up resistors on the dW/(RESET) line must not be smaller than 10k. The pull-up resistor is not required for debugWIRE functionality. • Connecting the RESET pin directly to VCC will not work. • Capacitors connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction.
AT90PWM2/3/2B/3B the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently.
AT90PWM2/3/2B/3B Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. 24.3.
AT90PWM2/3/2B/3B Figure 24-1. Read-While-Write vs.
AT90PWM2/3/2B/3B Figure 24-2.
AT90PWM2/3/2B/3B Table 24-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
AT90PWM2/3/2B/3B 24.5.1 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
AT90PWM2/3/2B/3B data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 0 – SPMEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles.
AT90PWM2/3/2B/3B Figure 24-3. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 24.7 1. The different variables used in Figure 24-3 are listed in Table 24-8 on page 279. Self-Programming the Flash The program memory is updated in a page by page fashion.
AT90PWM2/3/2B/3B 24.7.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. 24.7.2 • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
AT90PWM2/3/2B/3B 24.7.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
AT90PWM2/3/2B/3B value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 25-4 on page 282 for detailed description and mapping of the Extended Fuse byte. Bit 7 6 5 4 3 2 1 0 Rd – – – – EFB3 EFB2 EFB1 EFB0 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. 24.7.
AT90PWM2/3/2B/3B ;-It is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .
AT90PWM2/3/2B/3B Do_spm: ; check for previous SPM complete Wait_spm: in temp1, SPMCSR sbrc temp1, SPMEN rjmp Wait_spm ; input: spmcrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEPE rjmp Wait_ee ; SPM timed sequence out SPMCSR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret 24.7.
AT90PWM2/3/2B/3B For details about these two section, see “NRWW – No Read-While-Write Section” on page 267 and “RWW – Read-While-Write Section” on page 267 Table 24-8. Explanation of Different Variables used in Figure 24-3 and the Mapping to the Zpointer Corresponding Z-value(1) Variable Description PCMSB 11 Most significant bit in the Program Counter.
AT90PWM2/3/2B/3B 25. Memory Programming 25.1 Program And Data Memory Lock Bits The AT90PWM2/2B/3/3B provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 25-1.
AT90PWM2/3/2B/3B Table 25-3. Lock Bit Protection Modes(1)(2). BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
AT90PWM2/3/2B/3B 25.2 Fuse Bits The AT90PWM2/2B/3/3B has three Fuse bytes. Table 25-4 - Table 25-6 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 25-4.
AT90PWM2/3/2B/3B Table 25-5.
AT90PWM2/3/2B/3B 25.4 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. 25.4.1 Signature Bytes For the AT90PWM2/3 the signature bytes are: 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x93 (indicates 8KB Flash memory). 3. 0x002: 0x81 (indicates AT90PWM2/3 device when 0x001 is 0x93).
AT90PWM2/3/2B/3B Figure 25-1. Parallel Programming + 5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 VCC XA1 PAGEL + 12 V + 5V AVCC PB[7:0] PD6 DATA PD7 RESET BS2 PE2 XTAL1 GND Table 25-7.
AT90PWM2/3/2B/3B Table 25-9. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 25-10.
AT90PWM2/3/2B/3B 25.8 25.8.1 Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel (High-voltage) > Programming mode: 1. Set Prog_enable pins listed in Table 25-8. to “0000”, RESET pin to “0” and Vcc to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. Ensure that Vcc reaches at least 1.8V within the next 20µs. 3. Wait 20 - 60µs, and apply 11.5 - 12.5V to RESET. 4.
AT90PWM2/3/2B/3B 6. Wait until RDY/BSY goes high before loading a new command. 25.8.4 Programming the Flash The Flash is organized in pages, see Table 25-11 on page 286. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3.
AT90PWM2/3/2B/3B 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 25-3 for signal waveforms). I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse.
AT90PWM2/3/2B/3B 25.8.5 Programming the EEPROM The EEPROM is organized in pages, see Table 25-12 on page 286. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 288 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
AT90PWM2/3/2B/3B 25.8.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 288 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 25.8.
AT90PWM2/3/2B/3B Figure 25-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 25.8.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 288 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte.
AT90PWM2/3/2B/3B Figure 25-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte BS1 1 BS2 25.8.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 288 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”.
AT90PWM2/3/2B/3B Figure 25-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 25-9.
AT90PWM2/3/2B/3B Table 25-14.
AT90PWM2/3/2B/3B Figure 25-10. Serial Programming and Verify(1) +1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI_A AVCC MISO_A SCK_A XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.
AT90PWM2/3/2B/3B Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 25-15.
AT90PWM2/3/2B/3B Figure 25-11. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 25-16. Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Read Program Memory Byte 1 Byte 2 Byte 3 Byte4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
AT90PWM2/3/2B/3B Table 25-16. Serial Programming Instruction Set (Continued) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 25-5 on page 283 for details. 1010 1100 1010 0100 xxxx xxxx xxxx xxii Set bits = “0” to program, “1” to unprogram. See Table 25-4 on page 282 for details. 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1” = unprogrammed.
AT90PWM2/3/2B/3B 26. Electrical Characteristics(1) 26.1 Absolute Maximum Ratings* Operating Temperature.................................. -40C to +105C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1.0V to VCC+0.5V Voltage on RESET with respect to Ground......-1.0V to +13.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
AT90PWM2/3/2B/3B 26.2 DC Characteristics TA = -40C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. VIL Input Low Voltage Port B, C & D and XTAL1, XTAL2 pins as I/O VIH Input High Voltage Port B, C & D and XTAL1, XTAL2 pins as I/O VIL1 Input Low Voltage VIH1 VIL2 VIH2 Max. Units -0.5 0.2VCC(1) V 0.6VCC(2) VCC+0.5 V XTAL1 pin, External Clock Selected -0.5 0.1VCC(1) V Input High Voltage XTAL1 pin, External Clock Selected 0.7VCC(2) VCC+0.
AT90PWM2/3/2B/3B TA = -40C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Active 8 MHz, VCC = 3V, RC osc, PRR = 0xFF 3.8 7 mA Active 16 MHz, VCC = 5V, Ext Clock, PRR = 0xFF 14 24 mA Idle 8 MHz, VCC = 3V, RC Osc 1.5 3 mA Idle 16 MHz, VCC = 5V, Ext Clock 5.
AT90PWM2/3/2B/3B 5. Minimum VCC for Power-down is 2.5V. 6. The Analog Comparator Propagation Delay equals 1 comparator clock plus 30 nS. See “Analog Comparator” on page 227. for comparator clock definition. 26.3 26.3.1 External Clock Drive Characteristics Calibrated Internal RC Oscillator Accuracy Table 26-1. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25C ±10% User Calibration 7.3 - 8.1 MHz 2.7V - 5.
AT90PWM2/3/2B/3B 26.4 Maximum Speed vs. VCC Maximum frequency is depending on VCC. As shown in Figure 26-2, the Maximum Frequency equals 8Mhz when VCC is contained between 2.7V and 4.5V and equals 16Mhz when VCC is contained between 4.5V and 5.5V. Figure 26-2. Maximum Frequency vs. VCC, AT90PWM2/2B/3/3B 16Mhz 8Mhz Safe Operating Area 2.7V 26.5 4.5V 5.5V PLL Characteristics . Table 26-3. PLL Characteristics - VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Min. Typ. Max.
AT90PWM2/3/2B/3B 26.6 SPI Timing Characteristics See Figure 26-3 and Figure 26-4 for details. Table 26-4. SPI Timing Parameters Description Mode 1 SCK period Master See Table 17-4 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
AT90PWM2/3/2B/3B Figure 26-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
AT90PWM2/3/2B/3B 26.7 ADC Characteristics Table 26-5. Symbol ADC Characteristics - TA = -40C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted) Parameter Condition Min Typ Max Units Single Ended Conversion 10 Bits Differential Conversion 8 Bits Resolution Absolute accuracy Single Ended Conversion VREF = 2.56V ADC clock = 500 kHz 2.5 3 LSB Single Ended Conversion VREF = 2.56V ADC clock = 1MHz 6 (*) 7 LSB 20 LSB Single Ended Conversion VREF = 2.
AT90PWM2/3/2B/3B Table 26-5. Symbol ADC Characteristics - TA = -40C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Parameter Condition Min Typ Max Units Single Ended Conversion VCC = 4.5V, VREF = 4V ADC clock = 1MHz -4 0 LSB Single Ended Conversion VCC = 4.5V, VREF = 4V ADC clock = 500 kHz -2 2.5 LSB Differential Conversion VCC = 4.5V, VREF = 4V ADC clock = 1MHz -0.5 -0.5 LSB Differential Conversion VCC = 4.5V, VREF = 4V ADC clock = 500 kHz -0.5 -0.
AT90PWM2/3/2B/3B 26.9 Parallel Programming Characteristics Figure 26-5. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 26-6.
AT90PWM2/3/2B/3B Figure 26-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) DATA (Low Byte) ADDR1 (Low Byte) DATA (High Byte) XA0 XA1 Note: 1. ggThe timing requirements shown in Figure 26-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 26-7.
AT90PWM2/3/2B/3B Table 26-7. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter Min. tXLOL XTAL1 Low to OE Low 0 tBVDV BS1 Valid to DATA valid 0 tOLDV OE Low to DATA Valid Typ. Max. Units ns 250 ns 250 ns OE High to DATA Tri-stated 250 ns tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. tOHDZ Notes: 1.
AT90PWM2/3/2B/3B 27. AT90PWM2/2B/3/3B Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
AT90PWM2/3/2B/3B Figure 27-2. Active Supply Current vs. Frequency (1 - 24 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 30 25 5.5 V 5.0 V 20 ICC (mA) 4.5 V 15 4.0 V 10 3.3 V 3.0 V 5 2.7 V 0 0 5 10 15 20 25 Frequency (MHz) Figure 27-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs.
AT90PWM2/3/2B/3B Figure 27-4. Active Supply Current vs. VCC (Internal PLL Oscillator, 16 MHz) ACTIVE SUPPLY CURRENT vs. V CC INTERNAL PLL OSCILLATOR, 16 MHz 20 105 °C 85 °C 25 °C -40 °C 18 16 14 ICC (mA) 12 10 8 6 4 2 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) 27.2 Idle Supply Current Figure 27-5. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0,45 0,4 5.5 V ICC (mA) 0,35 5.0 V 0,3 4.5 V 0,25 4.0 V 0,2 3.3 V 3.0 V 2.
AT90PWM2/3/2B/3B Figure 27-6. Idle Supply Current vs. Frequency (1 - 24 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 12 10 5.5 V 5.0 V 8 ICC (mA) 4.5 V 6 4.0 V 4 3.3 V 3.0 V 2 2.7 V 0 -1 1 3 5 7 9 11 13 15 17 19 21 23 25 Frequency (MHz) Figure 27-7. IIdle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs.
AT90PWM2/3/2B/3B Figure 27-8. Idle Supply Current vs. VCC (Internal PLL Oscillator, 16 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL PLL OSCILLATOR, 16 MHz 9 105 °C 85 °C 25 °C -40 °C 8 7 ICC (mA) 6 5 4 3 2 1 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) 27.2.1 Using the Power Reduction Register The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
AT90PWM2/3/2B/3B Table 27-2. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 27-1 and Figure 27-2) Additional Current consumption compared to Idle with external clock (see Figure 27-5 and Figure 27-6) PRPSC2 10% 25% PRPSC1 10% 25% PRPSC0 10% 25% PRTIM1 8.5% 22% PRTIM0 4.3% 11% PRSPI 5.3% 14% PRUSART 15.6 36 PRADC 10.
AT90PWM2/3/2B/3B 27.3 Power-Down Supply Current Figure 27-9. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 7 105 °C 6 ICC (uA) 5 4 3 85 °C 2 -40 °C 25 °C 1 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 27-10. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs.
AT90PWM2/3/2B/3B 27.4 Pin Pull-up Figure 27-11. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN (including PE1 & PE2) PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5.0 V -40 °C 160 25 °C 85 °C 140 105 °C 120 100 IOP (uA) 80 60 40 20 0 0 1 2 3 4 5 6 -20 V OP (V) Figure 27-12. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN (including PE1 & PE2) PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.
AT90PWM2/3/2B/3B Figure 27-13. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V) PE0 and RESET PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5.0 V 25 °C 120 -40 °C 85 °C 105 °C 100 IOP (uA) 80 60 40 20 0 0 1 2 3 4 5 6 V OP (V) Figure 27-14. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) PE0 and RESET PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.
AT90PWM2/3/2B/3B 27.5 Pin Driver Strength Figure 27-15. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN (including PE1 & PE2) SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5.0 V 25 85 °C 25 °C -40 °C 20 IOH (mA) 105 °C 15 10 5 0 4 4,2 4,4 4,6 4,8 5 5,2 V OH (V) Figure 27-16. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN (including PE1 & PE2) SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.
AT90PWM2/3/2B/3B Figure 27-17. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN (including PE1 & PE2) SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5.0 V 25 -40 °C25 °C 85 °C105 °C 20 IOL (mA) 15 10 5 0 0 0,2 0,4 0,6 0,8 1 -5 V OL (V) Figure 27-18. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN (including PE1 & PE2) SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.
AT90PWM2/3/2B/3B 27.6 Pin Thresholds and Hysteresis Figure 27-19. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read As '1') I/O PIN (including PE1 & PE2) INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2,5 -40 °C 25 °C 85 °C 105 °C Threshold (V) 2 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 27-20. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0') I/O PIN (including PE1 & PE2) INPUT THRESHOLD VOLTAGE vs.
AT90PWM2/3/2B/3B Figure 27-21. I/O Pin Input HysteresisVoltage vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.6 -40 C 0.5 25 C Input Hysteresis ( V) 0.4 85 C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-22. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1') RESET INPUT THRESHOLD VOLTAGE vs.
AT90PWM2/3/2B/3B Figure 27-23. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 105 °C 85 °C 25 °C -40 °C 2,5 Threshold (V) 2 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 27-24. Reset Input Pin Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs.
AT90PWM2/3/2B/3B Figure 27-25. XTAL1 Input Threshold Voltage vs. VCC (XTAL1 Pin Read As '1') XTAL1 INPUT THRESHOLD VOLTAGE vs. VCC XTAL1 PIN READ AS "1" 4 3,5 -40 °C 25 °C 85 °C 105 °C Threshold (V) 3 2,5 2 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 27-26. XTAL1 Input Threshold Voltage vs. VCC (XTAL1 Pin Read As '0') XTAL1 INPUT THRESHOLD VOLTAGE vs.
AT90PWM2/3/2B/3B Figure 27-27. PE0 Input Threshold Voltage vs. VCC (PE0 Pin Read As '1') PE0 INPUT THRESHOLD VOLTAGE vs. VCC VIH, PE0 PIN READ AS '1' -40 °C 25 °C 85 °C 105 °C 4 3,5 Threshold (V) 3 2,5 2 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 27-28. PE0 Input Threshold Voltage vs. VCC (PE0 Pin Read As '0') PE0 INPUT THRESHOLD VOLTAGE vs.
AT90PWM2/3/2B/3B 27.7 BOD Thresholds and Analog Comparator Offset Figure 27-29. BOD Thresholds vs. Temperature (BODLEVEL Is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLV IS 4.3 V 4,42 Rising Vcc 4,4 Threshold (V) 4,38 4,36 4,34 Falling Vcc 4,32 4,3 4,28 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (C) Figure 27-30. BOD Thresholds vs. Temperature (BODLEVEL Is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLV IS 2.
AT90PWM2/3/2B/3B Figure 27-31. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC=5V) ANALOG COMPARATOR TYPICAL OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5.0 V 0,14 Analog comparator offset voltage (V) 0,12 0,1 0,08 0,06 0,04 0,02 0 0 1 2 3 4 5 6 Common Mode Voltage (V) Note: corrected on AT90PWM2B/3B to allow almost full scale use. Figure 27-32. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC=3V) ANALOG COMPARATOR TYPICAL OFFSET VOLTAGE vs.
AT90PWM2/3/2B/3B 27.8 Analog Reference Figure 27-33. AREF Voltage vs. VCC AREF VOLTAGE vs. VCC 2,6 105 °C 85 °C 25 °C 2,55 -40 °C Aref (V) 2,5 2,45 2,4 2,35 2,3 2 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Figure 27-34. AREF Voltage vs. Temperature AREF VOLTAGE vs. TEMPERATURE 2.59 2.58 5.5 5 4.5 3 Aref (V) 2.57 2.56 2.55 2.54 2.53 2.
AT90PWM2/3/2B/3B 27.9 Internal Oscillator Speed Figure 27-35. Watchdog Oscillator Frequency vs. VCC 110 108 106 FRC (kHz) -40 °C 104 25 °C 102 100 85 °C 98 105 °C 96 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 27-36. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10000 Cycles sampled w ith 250nS 8.4 8.3 8.2 OSCCAL (MHz) 8.1 8 2.7 7.9 5 7.8 7.7 7.6 7.5 7.
AT90PWM2/3/2B/3B Figure 27-37. Calibrated 8 MHz RC Oscillator Frequency vs. VCC INT RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 10000 Cycles sampled w ith 250nS 8.5 8.4 8.3 FRC (MHz) 8.2 105 8.1 85 8 25 7.9 -40 7.8 7.7 7.6 7.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 27-38. Calibrated 8 MHz RC Oscillator Frequency vs.
AT90PWM2/3/2B/3B 27.10 Current Consumption of Peripheral Units Figure 27-39. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 45 40 35 ICC (uA) 30 105 °C 85 °C 25 °C -40 °C 25 20 15 10 5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 27-40. ADC Current vs. VCC (ADC at 50 kHz) AREF vs. VCC ADC AT 50 KHz 500 450 -40 °C ICC (uA) 400 350 TE 300 250 TO 200 B L MP E AT HA C E C RA T IZE R E D 25 °C 85 °C 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
AT90PWM2/3/2B/3B Figure 27-41. Aref Current vs. VCC (ADC at 1 MHz) AREF vs. VCC ADC AT 1 MHz 180 85 ˚C 25 ˚C -40 ˚C 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-42. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs.
AT90PWM2/3/2B/3B Figure 27-43. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 14 -40 ˚C 12 ICC (mA) 10 25 ˚C 8 85 ˚C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 27.11 Current Consumption in Reset and Reset Pulse width Figure 27-44. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP ICC (mA) 0,18 0,16 5.5 V 0,14 5.0 V 0,12 4.5 V 0,1 4.0 V 0,08 3.3 V 3.0 V 2.
AT90PWM2/3/2B/3B Figure 27-45. Reset Supply Current vs. VCC (1 - 24 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 4 5.5 V 3,5 5.0 V 3 4.5 V ICC (mA) 2,5 2 4.0 V 1,5 3.3 V 1 3.0 V 2.7 V 0,5 0 0 5 10 15 20 25 Frequency (MHz) Figure 27-46. Reset Supply Current vs. VCC (Clock Stopped, Excluding Current through the Reset Pull-up) RESET CURRENT vs.
AT90PWM2/3/2B/3B Figure 27-47. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs.
AT90PWM2/3/2B/3B 28.
AT90PWM2/3/2B/3B Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBE) Reserved – – – – – – – – Page (0xBD) Reserved – – – – – – – – (0xBC) Reserved – – – – – – – – (0xBB) Reserved – – – – – – – – (0xBA) Reserved – – – – – – – – (0xB9) Reserved – – – – – – – – (0xB8) Reserved – – – – – – – – (0xB7) Reserved – – – – – – – – (0xB6) Reserved – – – – – – – – (0xB5) Reserved – – – – – – – –
AT90PWM2/3/2B/3B Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 247 (0x7B) ADCSRB ADHSM – – ADASCR ADTS3 ADTS2 ADTS1 ADTS0 page 249 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 248 (0x79) ADCH - / ADC9 - / ADC8 - / ADC7 - / ADC6 - / ADC5 - / ADC4 ADC9 / ADC3 ADC8 / ADC2 page 251 (0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 ADC5 / - ADC4 / - ADC3 / - ADC2 / - AD
AT90PWM2/3/2B/3B Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1A (0x3A) GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 page 27 0x19 (0x39) GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 page 27 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) Reserved – – – – – – – – 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 page 130 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV
AT90PWM2/3/2B/3B 29.
AT90PWM2/3/2B/3B Mnemonics Operands Description Operation Flags #Clocks BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0)
AT90PWM2/3/2B/3B Mnemonics Operands Description NOP No Operation SLEEP Sleep WDR BREAK Watchdog Reset Break Operation Flags #Clocks None 1 (see specific descr. for Sleep function) None 1 (see specific descr.
AT90PWM2/3/2B/3B 30. Ordering Information Speed (MHz) Power Supply Ordering Code Package 16 2.7 - 5.5V AT90PWM3-16SQ SO32 16 2.7 - 5.5V AT90PWM3-16MQT QFN32 16 2.7 - 5.5V AT90PWM3-16MQ QFN32 16 2.7 - 5.5V AT90PWM2-16SQ SO24 16 2.7 - 5.5V AT90PWM3B-16SE SO32 Operation Range Extended (-40C to 105C) Extended (-40C to 105C) Extended (-40C to 105C) Extended (-40C to 105C) Engineering Samples 16 2.7 - 5.5V AT90PWM3B-16ME QFN32 Engineering Samples 16 2.7 - 5.
AT90PWM2/3/2B/3B 31.
AT90PWM2/3/2B/3B 31.
AT90PWM2/3/2B/3B 31.
AT90PWM2/3/2B/3B 31.
AT90PWM2/3/2B/3B 350 4317K–AVR–03/2013
AT90PWM2/3/2B/3B 32. Errata 32.1 AT90PWM2&3 Rev.
AT90PWM2/3/2B/3B 5. PSC: Output Polarity in Centered Mode In centered mode, PSCOUTn1 outputs are not inverted, so they are active at the same time as PSCOUTn0. Workaround: Use an external inverter (or a driver with inverting output) to drive the load on PSCOUTn1. 6. PSC : POACnA/B Output Activity These register bits are not implemented in rev A. Workaround: Do not use this feature. 7. VREF Remark: To have Internal Vref on AREF pin select an internal analog feature such as DAC or ADC.
AT90PWM2/3/2B/3B 14. Analog comparator: Output signal The comparator output toggles at the comparator clock frequency when the voltage difference between both inputs is lower than the offset. This may occur when comparing signal with small slew rate. Work around: This effect normally do not impact the PSC, as the transition is sampled once per PSC cycle Be carefull when using the comparator as an interrupt source. 15.
AT90PWM2/3/2B/3B Work around: . Use, when Vcc=5V, Vref below Vcc-1V. Or, when Vref=Vcc=5V, do not uses codes above 800. 4. DAC Update in Autotrig mode If the cpu writes in DACH register at the same instant that the selected trigger source occurs and DAC Auto Trigger is enabled, the DACH register is not updated by the new value. Work around: . When using the autotrig mode, write twice in the DACH register. The time between the two CPU writes, must be different than the trigger source frequency.
AT90PWM2/3/2B/3B 33. Datasheet Revision History for AT90PWM2/2B/3/3B Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 33.1 Changes from 4317A- to 4317B 1. PSC section has been rewritten. 2. Suppression of description of RAMPZ which does not exist. 33.2 Changes from 4317B- to 4317C 1. Added AT90PWM2B/3B Advance Information. 2. Various updates throughout the document. 33.
AT90PWM2/3/2B/3B 3. PSC : the Balance Flank Width Modulation is done On-Time 1 rather than On-Time 0 (correction of figures) 4. Updated “Maximum Speed vs. VCC” on page 304 (formulas are removed) 5. Update of the “Errata” on page 351 33.8 Changes from 4317H to 4317I 1. Updated “History” on page 2 2. Updated “Device Clocking Options Select AT90PWM2B/3B” on page 31 3. Updated “Start-up Times when the PLL is selected as system clock” on page 35 4. Updated “ADC Noise Canceler” on page 241 5.
33.10 Changes from 4317J to 4317K 1. Applied the Atmel new brand template that includes new logo and new addresses. 2. Updated the Figure 3-1 on page 3. Pin 18 changed to AGND instead of GND. 3. Updated the Figure 3-2 on page 3. Pin 24 changed to AGND instead of GND. 4. Added note to the MLF/QFN package: The Center GND PADDLE has to be connected to GND. 5. Updated Figure 7-3 on page 32. 6. Updated Table 9-1 on page 47. Added VPOR and VCCRR characteristics. 7.
AT90PWM2/3/2B/3B Table of Contents 1 History 2 2 Disclaimer 2 3 Pin Configurations 3 3.1 4 5 6 7 Pin Descriptions 5 Overview 7 4.1 Block Diagram 8 4.2 Pin Descriptions 9 4.3 About Code Examples 10 AVR CPU Core 11 5.1 Introduction 11 5.2 Architectural Overview 11 5.3 ALU – Arithmetic Logic Unit 12 5.4 Status Register 13 5.5 General Purpose Register File 14 5.6 Stack Pointer 15 5.7 Instruction Execution Timing 15 5.8 Reset and Interrupt Handling 16 Memories 19 6.
AT90PWM2/3/2B/3B 8 9 7.9 Clock Output Buffer 38 7.10 System Clock Prescaler 38 Power Management and Sleep Modes 41 8.1 Sleep Mode Control Register – SMCR 41 8.2 Idle Mode 41 8.3 ADC Noise Reduction Mode 42 8.4 Power-down Mode 42 8.5 Standby Mode 42 8.6 Power Reduction Register 43 8.7 Minimizing Power Consumption 44 System Control and Reset 46 9.1 Internal Voltage Reference 50 9.2 Watchdog Timer 52 10 Interrupts 57 10.1 Interrupt Vectors in AT90PWM2/2B/3/3B 57 11 I/O-Ports 62 11.
AT90PWM2/3/2B/3B 14.8 8-bit Timer/Counter Register Description 97 15 16-bit Timer/Counter1 with PWM 104 15.1 Overview 104 15.2 Accessing 16-bit Registers 106 15.3 Timer/Counter Clock Sources 109 15.4 Counter Unit 110 15.5 Input Capture Unit 111 15.6 Output Compare Units 112 15.7 Compare Match Output Unit 114 15.8 Modes of Operation 115 15.9 Timer/Counter Timing Diagrams 123 15.10 16-bit Timer/Counter Register Description 124 16 Power Stage Controller – (PSC0, PSC1 & PSC2) 131 16.
AT90PWM2/3/2B/3B 16.23 PSC Clock Sources 161 16.24 Interrupts 162 16.25 PSC Register Definition 163 16.26 PSC2 Specific Register 172 17 Serial Peripheral Interface – SPI 175 17.1 Features 175 17.2 SS Pin Functionality 179 17.3 Data Modes 183 18 USART 185 18.1 Features 185 18.2 Overview 185 18.3 Clock Generation 186 18.4 Serial Frame 189 18.5 USART Initialization 190 18.6 Data Transmission – USART Transmitter 191 18.7 Data Reception – USART Receiver 194 18.
AT90PWM2/3/2B/3B 21.4 Prescaling and Conversion Timing 237 21.5 Changing Channel or Reference Selection 239 21.6 ADC Noise Canceler 241 21.7 ADC Conversion Result 245 21.8 ADC Register Description 247 21.9 Amplifier 252 21.10 Amplifier Control Registers 256 22 Digital to Analog Converter - DAC 259 22.1 Features 259 22.2 Operation 260 22.3 Starting a Conversion 260 22.4 DAC Register Description 261 23 debugWIRE On-chip Debug System 264 23.1 Features 264 23.2 Overview 264 23.
AT90PWM2/3/2B/3B 25.8 Parallel Programming 287 25.9 Serial Downloading 295 26 Electrical Characteristics(1) 300 26.1 Absolute Maximum Ratings* 300 26.2 DC Characteristics 301 26.3 External Clock Drive Characteristics 303 26.4 Maximum Speed vs. VCC 304 26.5 PLL Characteristics 304 26.6 SPI Timing Characteristics 305 26.7 ADC Characteristics 307 26.8 DAC Characteristics 308 26.9 Parallel Programming Characteristics 309 27 AT90PWM2/2B/3/3B Typical Characteristics 312 27.
AT90PWM2/3/2B/3B 33 Datasheet Revision History for AT90PWM2/2B/3/3B 355 33.1 Changes from 4317A- to 4317B 355 33.2 Changes from 4317B- to 4317C 355 33.3 Changes from 4317C- to 4317D 355 33.4 Changes from 4317D to 4317E 355 33.5 Changes from 4317E to 4317F 355 33.6 Changes from 4317F to 4317G 355 33.7 Changes from 4317G to 4317H 355 33.8 Changes from 4317H to 4317I 356 33.9 Changes from 4317I to 4317J 356 33.
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