Datasheet

96
7734Q–AVR–02/12
AT90PWM81/161
Figure 11-6. Timer/counter timing diagram, no prescaling.
Figure 11-7 shows the count sequence close to MAX in various modes.
Figure 11-7. Timer/counter timing diagram, no prescaling.
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
Tn
(clk
I/O
/1)
clk
I/O
ICFn
TOVn
TCNTn
BOTTOM BOTTOM + 1
clk
Tn
(clk
I/O
/1)
clk
I/O
MAX-1
MAX