Datasheet

86
7734Q–AVR–02/12
AT90PWM81/161
Figure 11-1. 16-bit timer/counter block diagram
(1)
.
Note: 1. Refer to Table 2-1 on page 5 for Timer/Counter1 pin placement and description.
11.1.1 Registers
The Timer/Counter (TCNT1), and Input Capture Register (ICR1) are all 16-bit registers. Special
procedures must be followed when accessing the 16-bit registers. These procedures are
described in the section “Accessing 16-bit Registers” on page 87. The Timer/Counter Control
Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt
requests (abbreviated to Int.Req. in Figure 11-1) signals are all visible in the Timer Interrupt Flag
Register (TIFR1). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK1). TIFR1 and TIMSK1 are not shown in Figure 11-1.
The Timer/Counter can be clocked internally, or by an external clock source on the T1 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to incre-
ment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected.
The output from the Clock Select logic is referred to as the timer clock (clk
T
1
).
The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-
gered) event on either the Input Capture pin (ICP1). The Input Capture unit includes a digital
filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
Clock Select
Timer/Counter
DATA BUS
ICRn
TCNTn
Noise
Canceler
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
TOVn
(Int.Req.)
ICFn (Int.Req.)
TCCRnB
Tn
Edge
Detector
(Ckio )
clk
Tn
ICPn
( From Analog
Comparator Ouput )
AC1ICE