Datasheet

7734Q–AVR–02/12

AT90PWM81/161

10. External Interrupts

The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts

will trigger even if the INT2:0 pins are configured as outputs. This feature provides a way of gen-

erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or

a low level. This is set up as indicated in the specification for the External Interrupt Control Reg-

isters – EICRA (INT2:0). When the external interrupt is enabled and is configured as level

triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or

rising edge interrupts on INT2:0 requires the presence of an I/O clock, described in “Clock Sys-

tems and their Distribution” on page 27. The I/O clock is halted in all sleep modes except Idle

mode.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. This makes the MCU less sensitive to

noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the

Watchdog Oscillator is 1µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-

tor is voltage dependent as shown in the “Electrical Characteristics (1)” on page 265. The MCU

will wake up if the input has the required level during this sampling or if it is held until the end of

the start-up time. The start-up time is defined by the SUT fuses as described in “System Clock

and Clock Options” on page 27. If the level is sampled twice by the Watchdog Oscillator clock

but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will

be generated. The required level must be held long enough for the MCU to complete the wake

up to trigger the level interrupt.

10.0.1 EICRA - External Interrupt Control Register A

• Bits 7..0 – ISC21, ISC20 – ISC01, ISC00: External Interrupt 2 - 0 Sense Control Bits

The External Interrupts 3 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 10-1. Edges on INT3..INT0 are registered asynchro-

nously.The value on the INT2:0 pins are sampled before detecting edges. If edge or toggle

interrupt is selected, pulses that last longer than one clock period will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency

can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is

selected, the low level must be held until the completion of the currently executing instruction to

generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as

long as the pin is held low.

Bit 76543210

- - ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 10-1. Interrupt sense Ccntrol

(1)

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request

0 1 Any logical change on INTn generates an interrupt request

1 0 The falling edge between two samples of INTn generates an interrupt request

1 1 The rising edge between two samples of INTn generates an interrupt request