Datasheet

79
7734Q–AVR–02/12
AT90PWM81/161
• ADC1/ACMP2_OUT, Bit 3
ADC1: Analog to Digital Converter, input channel 1.
ACMP2_OUT: Analog Comparator 2 Output.
•ADC0/ACMP1, Bit 2
ADC0: Analog to Digital Converter, input channel 0
.
ACMP1: Analog Comparator 1 Positive Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Ana-
log Comparator.
• PSCOUTR0/PSCINrB – Bit 1
PSCOUTR0: Output 0 of PSCR.
PCSINrB: PSCR Second Alternate Digital Input.
• ACMP3_OUT_A/SS
/CLKO – Bit 0
ACMP2_OUT_A: Analog Comparator 2 Alternate Output.
SS
: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDDn. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDDn.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTDn bit.
CLKO: Divided System Clock: The divided system clock can be output on this pin. The divided
system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTDn and
DDDn settings. It will also be output during reset.
Table 9-7 and Table 9-8 on page 80 relates the alternate functions of Port D to the overriding
signals shown in Figure 9-5 on page 73.
Table 9-7. Overriding signals for alternate functions PD7..PD4.
Signal name
PD7/ADC10/
PSCINrA PD6/APM0+ PD5/AMP0-/ADC7
PD4/ACMP3M/
ADC4/PSCIN2A
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0 0 0 0
PVOV 0 0 0 0
DIEOE ADC10D AMP0+D ADC7D ADC4D
DIEOV 0 0 0 0
DI PSCiNrA - - PSCIN2A
AIO ADC10 AMP0+ ADC7/AMP0- ADC4/ACMP3M