Datasheet

63
7734Q–AVR–02/12
AT90PWM81/161
the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the
Boot section or vice versa.
Note: 1. The Boot Reset Address is shown in Table 20-7 on page 246. For the BOOTRST Fuse “1”
means unprogrammed while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
AT90PWM81 is:
(for AT90PWM161, interrupt vector address have an increment equal to 2 in place of 1 for
AT90PWM81)
Address Labels Code Comments
0x000 rjmp RESET ; Reset Handler
0x001 rjmp PSC2_CAPT ; PSC2 Capture event Handler
0x002 rjmp PSC2_EC ; PSC2 End Cycle Handler
0x003 rjmp PSC2_EEC ; PSC2 End Enhanced Cycle Handler
0x004 rjmp PSCR_CAPT ; PSCr Capture event Handler
0x005 rjmp PSCR_EC ; PSC0 End Cycle Handler
0x006 rjmp PSCR_EEC ; PSCr End Enhanced Cycle Handler
0x007 rjmp ANA_COMP_0 ; Analog Comparator 0 Handler
0x008 rjmp ANA_COMP_1 ; Analog Comparator 1 Handler
0x009 rjmp ANA_COMP_2 ; Analog Comparator 2 Handler
0x00A rjmp EXT_INT0 ; IRQ0 Handler
0x00B rjmp TIM1_CAPT ; Timer1 Capture Handler
0x00C rjmp TIM1_OVF ; Timer1 Overflow Handler
0x00D rjmp ADC ; ADC Conversion Complete Handler
0x00E rjmp EXT_INT1 ; IRQ1 Handler
0x00F rjmp SPI_STC ; SPI Transfer Complete Handler
0x010 rjmp EXT_INT2 ; IRQ2 Handler
0x011 rjmp WDT ; Watchdog Timer Handler
0x012 rjmp EE_RDY ; EEPROM Ready Handler
0x013 rjmp SPM_RDY ; Store Program Memory Ready Handler
0x014 rjmp
0x015 rjmp
0x016 rjmp
0x017 rjmp
0x018 rjmp
0x019 rjmp
0x01A rjmp
0x01B rjmp
Table 8-2. Reset and interrupt vectors placement in AT90PWM81/161
(1)
.
BOOTRST IVSEL Reset address Interrupt vectors start address
1 0 0x000 0x001
1 1 0x000 Boot reset address + 0x001
0 0 Boot reset address 0x001
0 1 Boot reset address Boot reset address + 0x001