Datasheet

51
7734Q–AVR–02/12
AT90PWM81/161
Figure 7-1. Reset logic.
Notes: 1. Values are guidelines only.
2. The power-on reset will not work unless the supply voltage has been below V
POT
(falling).
7.1.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 7-1. The POR is activated whenever V
CC
is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
CC
rise. The RESET signal is activated again, without any delay,
when V
CC
decreases below the detection level.
Table 7-1. Reset characteristics
(1)
.
Symbol Parameter Condition Minimum Typical Maximum Units
V
POT
Power-on reset threshold
voltage (rising)
1.4 2.3 V
Power-on reset threshold
voltage (falling)
(2)
1.3 2.3 V
V
RST
RESET pin threshold voltage 0.2V
CC
0.85V
CC
V
t
RST
Minimum pulse width on
RESET
pin
400 ns
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BU S
Clock
Generator
Spike
Filter
Pull-up Resistor
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
RSTDIS