Datasheet

7734Q–AVR–02/12

AT90PWM81/161

be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “I/O-Ports” on page 68 for details on which pins are enabled. If the

input buffer is enabled and the input signal is left floating or have an analog signal level close to

/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V

/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to “DIDR1 - Digital Input Disable Register 1” on page 222 and “DIDR0 - Digital

Input Disable Register 0” on page 202 for details.

6.7.7 On-chip Debug System

If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the

main clock source is enabled, and hence, always consumes power. In the deeper sleep modes,

this will contribute significantly to the total current consumption.

6.8 Register description

6.8.1 SMCR - Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 6-2.

Note: 1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 1 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

Bit 76543210

– – – – SM2 SM1 SM0 SE SMCR

Read/Write RRRRR/WR/WR/WR/W

Initial Value00000000

Table 6-2. Sleep mode select.

SM2 SM1 SM0 Sleep mode

000Idle

0 0 1 ADC noise reduction

010Power-down

011Reserved

100Reserved

101Reserved

110Standby

(1)

111Reserved