Datasheet

43
7734Q–AVR–02/12
AT90PWM81/161
the clock frequency and, of course, if the clock is alive. The user’s has itself to do the difference
between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’.
• Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0
These bits define the command to provide to the ‘Clock Switch’ module. The special write
procedure must be followed to change the CLKC bits (see “Bit 7 – CLKCCE: Clock Control Change
Enable” on page 42).
1. Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in
CLKCSR to zero.
2. Within four cycles, write the desired value to CLKCSR register while clearing CLKCCE
bit.
Interrupts should be disabled when setting CLKCSR register in order not to disturb the
procedure.
5.5.6 CLKSELR - Clock Selection Register
• Bit 7– Res: Reserved Bit
This bit is reserved bit in the AT90PWM81/161 and will always read as zero.
• Bit 6 – COUT: Clock Out
The COUT bit is initialized with CKOUT Fuse bit.
The COUT bit is only used in case of ‘CKOUT’ command. Refer to Section 5.2.7 ”Clock Output
Buffer” on page 34 for using.
In case of ‘Recover System Clock Source’ command, COUT it is not affected (no recovering of
this setting).
• Bits 5:4 – CSUT1:0: Clock Start-up Time
CSUT bits are initialized with the values of SUT Fuse bits.
In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock
start-up time. Refer to subdivisions of Section 5.2 ”Clock Sources” on page 28 for code of clock
Table 5-12. Clock command list.
Clock command CLKC3..0
No command 0000
b
Disable clock source 0001
b
Enable clock source 0010
b
Request for clock availability 0011
b
Clock source switch 0100
b
Recover system clock source code 0101
b
CKOUT command 0111
b
No command 1xxx
b
Bit 7 6 543210
- COUT CSUT1 CSUT0 CSEL3 CSEL2 CSEL1 CSEL0 CLKSELR
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 CKOUT
fuse
SUT1..0
fuses
CKSEL3..0
fuses