Datasheet

41
7734Q–AVR–02/12
AT90PWM81/161
5.5.3 PLLCSR - PLL Control and Status Register
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM81/161 and always read as zero.
• Bit 5..2-– PLLF: PLL Factor
The PLLF bits is used to select the multiplication factor of the PLL.
Note: PLLF3 is used for debug purpose (must be wired).
0101 32
0110 64
0111 128
1000 256
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
Table 5-10. Clock prescaler select. (Continued)
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock division factor
Bit 76543210
$29 ($29) – – PLLF3 PLLF2 PLLF1 PLLF0 PLLE PLOCK PLLCSR
Read/Write R R R/W R/W R/W R/W R/W R
Initial Value 0 0 0 1 0 0 0/1 0
Table 5-11. PLL multiplication factor.
PLLF3..0 N+2 PLL frequency [MHz]
7-F Reserved
68 64
57 56
46 48
35 40
24 32
0-1 Reserved