Datasheet

34
7734Q–AVR–02/12
AT90PWM81/161
The PLL is locked on the source oscillator which must remains close to 8MHz to assure proper
lock of the PLL.
Both internal RC Oscillator and PLL are switched off in Power-down and Standby sleep modes
Figure 5-4. PCK clocking system.
5.2.7 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse or COUT bit of CLKSELR register has to be programmed. This mode is suitable when the
chip clock is used to drive other circuits on the system. Note that the clock will not be output dur-
ing reset and the normal operation of I/O pin will be overridden when the fuses are programmed.
Any clock source can be selected when the clock is output on CLKO. If the System Clock Pres-
caler is used, it is the divided system clock that is output.
Table 5-9. Start-up times when the PLL is selected as system clock.
CKSEL3..0 SUT1..0
Start-up time from power-
down
Additional delay from reset
(V
CC
= 5.0V) Clock source
0100
00 1K CK 14CK
External crystal or
resonator
01 1K CK 14CK + 4ms
10 1K CK 14CK + 64ms
11 16K CK 14CK
0101
00 16K CK 14CK
External clock
01 16K CK 14CK + 4ms
10 16K CK 14CK + 4ms
11 16K CK 14CK + 64ms
0001
00 1K CK 14CK
Internal RC oscillator01 1K CK 14CK + 4ms
10 1K CK 14CK + 64ms
RC OSCILLATOR
OSCCAL
XTAL1
XTAL2
OSCILLATORS
CK
PLLE
Lock
Detect or
PLOCK
SO U RCE
DIVIDE
BY 4
CLK
PLL
CKSEL3..0
8MHz
PLL
*N
PLLF3..0