Datasheet

310
7734Q–AVR–02/12
AT90PWM81/161
7. ADC measurement reports abnormal values with PSC2-synchronized
conversions
When using ADC in synchronized mode, an unexpected extra Single ended conversion can
spuriously re-start.This can occur when the End of conversion and the Trigger event occur
at the same time.
Work around:
No workaround
8. Over-consumption in power down sleep mode.
In Power-down mode, an extra power consumption up to 500µA may occur.
Work around:
No workaround
27.4 Errata AT90PWM81 revD
• Clock Switch disable
• Crystal oscillator control with Clock Switch
• BOD disable fuse
• Flash and EEPROM programming failure if CPU clock is switched
• ADC Amplifier measurement is unstable
• ADC measurement reports abnormal values with PSC2-synchronized conversions
• Over-consumption in power down sleep mode
1. Clock Switch enable & disable
After a “Enable Clock Source” or a “Disable Clock Source” command, the command is still
active until the next access of CLKCSR register. If CLKSEL is written with a new value, the
corresponding clock will be unintentionnaly enabled or disabled.
Work around:
Atter the Enable or Disable command, write CLKCSR with value 1<<CLKCCE
2. Crystal oscillator control with Clock Switch
When a Xtal oscillator is active and CLKSELR is written with a new value for the selection of
another clock source (for instance RC or WD) , the Xtal oscillator gain is not correct.
Work around:
After the commands “Enable Clock Source” and “Clock Source Switching”, write back CLK-
SELR with the values corresponding to the active Xtal oscillator
3. BOD disable fuse
It is strongly advised to keep the BOD active. Indeed, the RC oscillator may lock if it is acti-
vated when the power suppy goes at a low voltage.
Work around:
If it is mandatory to disable the BOD, do not set the RC oscillator as clock source during
reset and makes sure the RC oscillator is never active when the power supply is below the
lowest POR voltage (2.6V).