Datasheet

302
7734Q–AVR–02/12
AT90PWM81/161
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ¬ PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ¬ PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ¬ PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ¬ 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ¬ 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ¬ Rd(n), Rd(0) ¬ 0 Z, C, N, V 1
LSR Rd Logical Shift Right Rd(n) ¬ Rd(n+1), Rd(7) ¬ 0 Z, C, N, V 1
ROL Rd Rotate Left Through Carry Rd(0)¬C,Rd(n+1)¬ Rd(n),C¬Rd(7) Z, C, N, V 1
ROR Rd Rotate Right Through Carry Rd(7)¬C,Rd(n)¬ Rd(n+1),C¬Rd(0) Z, C, N, V 1
ASR Rd Arithmetic Shift Right Rd(n) ¬ Rd(n+1), n=0..6 Z, C, N, V 1
SWAP Rd Swap Nibbles Rd(3..0)¬Rd(7..4),Rd(7..4)¬Rd(3..0) None 1
BSET s Flag Set SREG(s) ¬ 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ¬ 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ¬ Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ¬ T None 1
SEC Set Carry C ¬ 1 C 1
CLC Clear Carry C ¬ 0 C 1
SEN Set Negative Flag N ¬ 1 N 1
CLN Clear Negative Flag N ¬ 0 N 1
SEZ Set Zero Flag Z ¬ 1 Z 1
CLZ Clear Zero Flag Z ¬ 0 Z 1
SEI Global Interrupt Enable I ¬ 1 I 1
CLI Global Interrupt Disable I ¬ 0 I 1
SES Set Signed Test Flag S ¬ 1 S 1
CLS Clear Signed Test Flag S ¬ 0 S 1
SEV Set Twos Complement Overflow. V ¬ 1 V 1
CLV Clear Twos Complement Overflow V ¬ 0 V 1
SET Set T in SREG T ¬ 1 T 1
CLT Clear T in SREG T ¬ 0 T 1
SEH Set Half Carry Flag in SREG H ¬ 1 H 1
CLH Clear Half Carry Flag in SREG H ¬ 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ¬ Rr None 1
MOVW Rd, Rr Copy Register Word
Rd+1:Rd ¬ Rr+1:Rr
None 1
LDI Rd, K Load Immediate Rd ¬ K None 1
LD Rd, X Load Indirect Rd ¬ (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ¬ (X), X ¬ X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ¬ X - 1, Rd ¬ (X) None 2
LD Rd, Y Load Indirect Rd ¬ (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ¬ (Y), Y ¬ Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ¬ Y - 1, Rd ¬ (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ¬ (Y + q) None 2
LD Rd, Z Load Indirect Rd ¬ (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ¬ (Z), Z ¬ Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ¬ Z - 1, Rd ¬ (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ¬ (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ¬ (k) None 2
ST X, Rr Store Indirect (X) ¬ Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ¬ Rr, X ¬ X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ¬ X - 1, (X) ¬ Rr None 2
ST Y, Rr Store Indirect (Y) ¬ Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ¬ Rr, Y ¬ Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ¬ Y - 1, (Y) ¬ Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ¬ Rr None 2
ST Z, Rr Store Indirect (Z) ¬ Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ¬ Rr, Z ¬ Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ¬ Z - 1, (Z) ¬ Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ¬ Rr None 2
STS k, Rr Store Direct to SRAM (k) ¬ Rr None 2
LPM Load Program Memory R0 ¬ (Z) None 3
LPM Rd, Z Load Program Memory Rd ¬ (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ¬ (Z), Z ¬ Z+1 None 3
SPM Store Program Memory (Z) ¬ R1:R0 None -
IN Rd, P In Port Rd ¬ P None 1
OUT P, Rr Out Port P ¬ Rr None 1
Mnemonics Operands Description Operation Flags #Clocks