Datasheet

29
7734Q–AVR–02/12
AT90PWM81/161
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
2. PLL must be driven by a nominal 8MHz clock source.
3. Flash fuse bits.
4. CLKSELR register bits.
5. Ext Osc: External oscillator.
6. RC Osc: Internal RC oscillator (1MHz or 8MHz).
7. WD: Internal watch dog RC oscillator 128kHz.
8. Ext Clk: External clock input.
The various choices for each clocking option is given in the following sections.
When the CPU wakes up from Power-down, or when a new clock source is enabled by the
dynamic clock switch circuit, the selected clock source is used to time the start-up, ensuring sta-
ble oscillator operation before instruction execution starts.
When the CPU starts from reset, there is an additional delay allowing the power to reach a sta-
ble level before commencing normal operation. The Watchdog Oscillator is used for timing this
real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out
is shown in Table 5-2.
5.2.1 Default Clock Source
The device will always starts up from reset using the clock source defined by CKSEL Fuses the
start-up time defined by SUT Fuses. This configuration is latched in CLKSELR register at reset.
The device will always starts up at Power-on using the clock source defined by CLKSELR regis-
ter (CSEL3..0 and CSUT1:0).
The device is shipped with CKSEL Fuses = 0010
b
, SUT Fuses = 10
b
, and CKDIV8 Fuse pro-
grammed. The default clock source setting is therefore the Internal RC Oscillator running at
8MHz with longest start-up time and an initial system clock prescaling of 8. This default setting
ensures that all users can make their desired clock source setting using an In-System or High-
voltage Programmer. This set-up must be taken into account when using ISP tools.
5.2.2 Calibrated Internal RC Oscillator
By default, the Internal RC OScillator provides an approximate 8.0MHz clock or a 1MHz clock.
Though voltage and temperature dependent, this clock can be very accurately calibrated by the
user.
External crystal/ceramic resonator (3.0MHz - 8.0MHz) Ext Osc
(5)
RC Osc
(6)
1101
b
XTAL1 XTAL2
External crystal/ceramic resonator (8.0MHz - 16.0MHz) Ext Osc
(5)
RC Osc
(6)
1110
b
XTAL1 XTAL2
External crystal/ceramic resonator (8.0MHz - 16.0MHz) Ext Osc
(5)
RC Osc
(6)
1111
b
XTAL1 XTAL2
Table 5-1. Device clocking options select
(1)
, PLL source and PE1 and PE2 functionality. (Continued)
Device clocking option System
clock PLL input
(2)
CKSEL3..0
(3)
CSEL3..0
(4)
PE1 PE2
Table 5-2. Number of watchdog oscillator cycles.
Typical time-out Number of cycles
4ms 512
64ms 8K (8,192)