Datasheet

277
7734Q–AVR–02/12
AT90PWM81/161
Figure 22-6. Parallel programming timing, loading sequence with timing requirements
(1)
.
Note: 1. The timing requirements shown in Figure 22-5 on page 276 (that is, t
DVXH
, t
XHXL
, and t
XLDX
)
also apply to loading operation.
Figure 22-7. Parallel programming timing, reading sequence (within the same page) with timing requirements
(1)
.
Note: 1. The timing requirements shown in Figure 22-5 on page 276 (that is, t
DVXH
, t
XHXL
, and t
XLDX
)
also apply to reading operation.
XTAL1
XLXH
t
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
PAGEL/BS1
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
PAGEL/BS1
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ