Datasheet

273
7734Q–AVR–02/12
AT90PWM81/161
Figure 22-3. SPI interface timing requirements (Master mode).
Figure 22-4. SPI interface timing requirements (Slave mode).
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
6 1
22
34 5
8
7
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16