Datasheet

272
7734Q–AVR–02/12
AT90PWM81/161
Notes: 1. While connected to external clock or external oscillator, PLL Input Frequency must be selected
to provide outputs with frequency in accordance with driven parts of the circuit.
2. When V
CC
is below 4.5V, maximum PLL
F
is 6.
22.6 SPI Timing Characteristics
See Figure 22-3 on page 273 and Figure 22-4 on page 273 for details.
Notes: 1. In SPI programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
<12MHz
- 3 t
CLCL
for f
CK
>12MHz
Table 22-5. SPI timing parameters.
Description Mode Minimum Typical Maximum Units
1 SCK period Master
See Table 14-
5 on page 187
ns
2 SCK high/low Master 50% duty cycle
3 Rise/fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 • t
ck
11 SCK high/low
(1)
Slave 2 • t
ck
ns
12 Rise/fall time Slave 1.6
13 Setup Slave 10
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 2 • t
ck