Datasheet

261
7734Q–AVR–02/12
AT90PWM81/161
21.8 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET
is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET
is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 21-14 on page 254, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Figure 21-7. Serial programming and verify
(1)
.
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. V
CC
- 0.3V < AV
CC
< V
CC
+ 0.3V, however, AV
CC
should always be within 1.8V - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
>= 12MHz
High: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
>= 12MHz
21.8.1 Serial Programming Algorithm
When writing serial data to the AT90PWM81/161, data is clocked on the rising edge of SCK.
When reading data from the AT90PWM81/161, data is clocked on the falling edge of SCK. See
Figure 21-8 on page 263 for timing details.
To program and verify the AT90PWM81/161 in the serial programming mode, the following
sequence is recommended (see four byte instruction formats in Table 21-16 on page 263):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
VCC
GND
XTAL1
SCK_A
MISO_A
MOSI_A
RESET
+1.8V - 5.5V
AVCC
+1.8V - 5.5V
(2)