Datasheet

250
7734Q–AVR–02/12
AT90PWM81/161
PSCRV gives the state low or high which will be forced on PSC outputs selected by PSC0RB &
PSC2RB fuses.
If PSCRV fuse equals 0 (programmed), the selected PSC outputs will be forced to low state. If
PSCRV fuse equals 1 (unprogrammed), the selected PSC outputs will be forced to high state.
If PSCRRB fuse equals 1 (unprogrammed), PSCOUTR0 & PSCOUTR1 keep a standard port
behavior. If PSC0RB fuse equals 0 (programmed), PSCOUTR0 & PSCOUTR1 are forced at
reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUTR0 &
PSCOUTR1 keep the forced state until PSOC0 register is written.
If PSC2RB fuse equals 1 (unprogrammed), PSCOUT20 & PSCOUT21 keep a standard port
behavior. If PSC2RB fuse equals 0 (programmed), PSCOUT20 & PSCOUT21 are forced at
reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUT20 &
PSCOUT21 keep the forced state until PSOC2 register is written.
If PSC2RBA fuse equals 1 (unprogrammed), PSCOUT22 & PSCOUT23 keep a standard port
behavior. If PSC2RBA fuse equals 0 (programmed), PSCOUT22 & PSCOUT23 are forced at
reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUT22 &
PSCOUT23 keep the forced state until PSOC2 register is written.
21.2.2 PSC Input Behavior During Reset
For power consumption under reset reason, the state of PSC & PSCR inputs during Reset can
be programmed by fuse PSCINRB.
If PSCINRB fuse equals 1 (unprogrammed), PSC & PSCR input keep a standard port behavior.
If PSCINRB fuse equals 0 (programmed), PSC & PSCR input pull-up are forced while the reset
is active. Affected pins are PSCIN2, PSCINr, PSCIN2A, PSCINrA. To prevent any conflict on
PD1, this fuse has no effect on PSCINrB.
Notes: 1. See “Alternate Functions of Port E” on page 80 for description of RSTDISBL Fuse.
2. The SPIEN Fuse is not accessible in serial programming mode.
3. See “Watchdog timer configuration.” on page 60 for details.
4. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 21-8 on page 252
for details.
Table 21-5. Fuse High byte.
High Fuse byte Bit no. Description Default value
RSTDISBL
(1)
7 External reset disable 1 (unprogrammed)
DWEN 6 debugWIRE enable 1 (unprogrammed)
SPIEN
(2)
5
Enable serial program and data
downloading
0 (programmed, SPI
programming enabled)
WDTON
(3)
4 Watchdog timer always on 1 (unprogrammed)
EESAVE 3
EEPROM memory is preserved through
the chip erase
1 (unprogrammed), EEPROM
not reserved
BOOTSZ1 2
Select boot size
(see Table 20-7 on page 246 for details)
0 (programmed)
(4)
BOOTSZ0 1
Select boot size
(see Table 20-7 on page 246 for details)
0 (programmed)
(4)
BOOTRST 0 Select reset vector 1 (unprogrammed)