Datasheet

244
7734Q–AVR–02/12
AT90PWM81/161
Note: 1. TSGAIN typical value is 0x80=128
2. See Note 3
3. Final Test Amb V
REF
HIGH BYTE and LOW BYTE:
Typical values are for V
REF
= 2.56V:
HIGH BYTE = 0x0A
LOW BYTE = 0x00
This means:
Final Test Amb V
REF
= 0x0A00 = 2560 = V
REF
× 1000
4. See Note 3 which details the value format
5. See Note 3 which details the value format
20.7.11 Preventing Flash Corruption
During periods of low V
CC
, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader
Lock bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low V
CC
reset protection circuit
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low V
CC
. This will pre-
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
20.7.12 Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 20-6 shows the typical pro-
gramming time for Flash accesses from the CPU.
Final test amb V
REF
: HIGH BYTE
(3)
0x3D XXH XXH
Final test hot V
REF
: LOW BYTE (only a Read)
(4)
0x3E XXH XXH
Final test hot V
REF
: HIGH BYTE (only a Read)
(5)
0x3F XXH XXH
Table 20-5. Signature row addressing. (Continued)
Signature Byte Address
AT90PWM81
data
AT90PWM161
data
Table 20-6. SPM programming time.
Symbol Min. programming time Max. programming time
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
3.7ms 4.5ms