Datasheet

229
7734Q–AVR–02/12
AT90PWM81/161
• Bit 7 – DAATE: DAC Auto Trigger Enable bit (not useful, may be left for compatibility)
Set this bit to update the DAC input value on the positive edge of the trigger signal selected with
the DACTS2-0 bit in DACON register.
Clear it to automatically update the DAC input when a value is written on DACH register.
• Bit 6:4 – DATS2, DATS1, DATS0: DAC Trigger Selection bits (not useful, may be left for
compatibility)
These bits are only necessary in case the DAC works in auto trigger mode. It means if DAATE
bit is set.
In accordance with the Table 18-1, these 3 bits select the interrupt event which will generate the
update of the DAC input values. The update will be generated by the rising edge of the selected
interrupt flag whether the interrupt is enabled or not.
• Bit 2 – DALA: Digital to Analog Left Adjust
Set this bit to left adjust the DAC input data.
Clear it to right adjust the DAC input data.
The DALA bit affects the configuration of the DAC data registers. Changing this bit affects the
DAC output on the next DACH writing.
• Bit 1 – Reserved
• Bit 0 – DAEN: Digital to Analog Enable bit
Set this bit to enable the DAC.
Clear it to disable the DAC.
18.4.2 DACH and DACL - Digital to Analog Converter input Register
DACH and DACL registers contain the value to be converted into analog voltage.
Writing the DACL register forbid the update of the input value until DACH has not been written
too. So the normal way to write a 10-bit value in the DAC register is firstly to write DACL the
DACH.
In order to work easily with only 8 bits, there is the possibility to left adjust the input value. Like
this it is sufficient to write DACH to update the DAC value.
Table 18-1. DAC auto trigger source selection.
DATS2 DATS1 DATS0 Description
0 0 0 Analog comparator 0
0 0 1 Analog comparator 1
0 1 0 External Interrupt Request 0
011Reserved
100Reserved
101Reserved
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event