Datasheet

226

7734Q–AVR–02/12

AT90PWM81/161

• Bit 5, 4– AMP0G1, 0: Amplifier 0 Gain Selection Bits

These two bits determine the gain of the amplifier 0.

The different setting are shown in Table 17-7.

To ensure an accurate result, after the gain value has been changed, the amplifier input needs

to have a quite stable input value during at least four Amplifier synchronization clock periods.

• Bit 3– AMP0GS: Amplifier 0 Ground Select of AMP0

This bit select negative input of the amplifier:

Set this bit to ground the Amplifier 0 negative input.

Clear this bit to normally use the Amplifier 0 differential input.

• Bit 1, 0– AMP0TS1, AMP0TS0: Amplifier 0 Trigger Source Selection Bits

In accordance with the Table 17-8, these two bits select the event which will generate the trigger

for the amplifier 0. This trigger source is necessary to start the conversion on the amplified

channel.

Table 17-7. Amplifier 0 gain selection.

AMP0G1 AMP0G0 Description

00Gain 5

01Gain 10

10Gain 20

11Gain 40

Table 17-8. AMP0 auto trigger source selection.

AMP0TS1 AMP0TS0 Description

0 0 Auto synchronization on ADC Clock/8

0 1 Trig on PSCRASY

1 1 Trig on PSC2ASY