Datasheet

225
7734Q–AVR–02/12
AT90PWM81/161
The block diagram of the two amplifiers is shown on Figure 17-17.
Figure 17-17. Amplifiers block diagram.
If APMP0GS bit is set, the AMP0- input is open and PD5/AMP0- pin is free for another use. At
the same time the negative input of the Amplifier is internally grounded.
17.10 Amplifier Control Registers
The configuration of the amplifier is controlled via the register AMP0CSR. Then the start of con-
version is done via the ADC control and status registers.
The conversion result is stored on ADCH and ADCL register which contain respectively the most
significant bits and the least significant bits.
17.10.1 AMP0CSR - Amplifier 0 Control and Status register
• Bit 7 – AMP0EN: Amplifier 0 Enable Bit
Set this bit to enable the Amplifier 0.
Clear this bit to disable the Amplifier 0.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
• Bit 6– AMP0IS: Amplifier 0 Input Shunt
Set this bit to short-circuit the Amplifier 0 input. If AMP0GS is set, the ground switch is released
during shunt of inputs.
Clear this bit to normally use the Amplifier 0.
AMP0TS1 AMP0TS0AMP0EN AMP0IS AMP0G1 AMP0G0
AMP0CSR
+
-
SA M PL I N G
AMP0+
AMP0-
To w a r d A D C M U X
(AMP0)
Sa m p l i n g
Cl o ck
ADCK/ 8
01
10
00
-
1 1 PSC2ASY
PSCRASY
AMP0GS
no short
AMP0+ GND
Bit 7 6543210
AMP0EN AMP0IS AMP0G1 AMP0G0 AMP0GS - AMP0TS1 AMP0TS0 AMP0CSR
Read/Write R/W R/W R/W R/W - - R/W R/W
Initial Value 0 0 0 0 0 0 0 0