Datasheet

224
7734Q–AVR–02/12
AT90PWM81/161
Figure 17-15. Amplifier synchronization timing diagram with change on analog input signal.
Figure 17-16. Amplifier synchronization timing diagram: behavior when ADSC is set when the
amplifier output is changing.
Valid sample
Delta V
4th stable sample
Signal to be
measured
AMPLI_clk
(Sync Clock)
CK ADC
Ampli er Sample
Enable
Ampli er Hold
Value
PSCn_ASY
PSC
Block
Ampli er
Block
ADSC
ADC
Activity
ADC
ADC
Sampling
ADC
Conv
ADC
Sampling
ADC
Conv
ADC Result
Ready
ADC Resu
Ready
Valid sample
Signal to be
measured
AMPLI_clk
(Sync Clock)
CK ADC
Ampli er Sample
Enable
Ampli er Hold
Value
PSCn_ASY
PSC
Block
Ampli er
Block
ADSC
ADC
Activity
ADC
ADC
Sampling
ADC
Conv
ADC
Sampling
ADC
Conv
ADC
Sampling
Aborted
ADC Result
Ready
ADC Result
Ready