Datasheet

223
7734Q–AVR–02/12
AT90PWM81/161
Amplified conversions can be synchronized to PSC events (see “Synchronization source
description in one/two/four ramp modes.” on page 134 and “Synchronization source description
in centered mode.” on page 135) or to the internal clock CK
ADC
equal to eighth the ADC clock
frequency. In case the synchronization is done by the ADC clock divided by eight, this synchro-
nization is done automatically by the ADC interface in such a way that the sample-and-hold
occurs at a specific phase of CK
ADC2
. A conversion initiated by the user (that is, all single conver-
sions, and the first free running conversion) when CK
ADC2
is low will take the same amount of
time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A
conversion initiated by the user when CK
ADC2
is high will take 14 ADC clock cycles due to the
synchronization mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0 bits
in the AMPxCSR register. Then the amplifier can be switched on, and the amplification is done
on each synchronization event. The amplification is done independently of the ADC.
In order to start an amplified Analog to Digital Conversion on the amplified channel, the ADMUX
must be configured as specified on Table 17-4 on page 218.
The ADC starting is done by setting the ADSC (ADC Start conversion) bit in the ADCSRB
register.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
On AT90PWM81/161, conversion takes advantage of the amplifier characteristics to ensure
minimum conversion time.
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion
is started. In order to have a better understanding of the functioning of the amplifier synchroniza-
tion, a timing diagram example is shown Figure 17-15 on page 224.
In case the amplifier output is modified during the sample phase of the ADC, the on-going con-
version is aborted and restarted as soon as the output of the amplifier is stable as shown Figure
17-16 on page 224.
The only precaution to take is to be sure that the trig signal (PSC) frequency is lower than
ADCclk/4.
It is also possible to auto trigger conversion on the amplified channel. In this case, the conver-
sion is started at the next amplifier clock event following the last auto trigger event selected
thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running
mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.