Datasheet

222
7734Q–AVR–02/12
AT90PWM81/161
17.8.4.2 ADLAR = 1
17.8.5 DIDR0 - Digital Input Disable Register 0
• Bit 7:0 – ADC7D..ADC0D: AMP0-D and ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
17.8.6 DIDR1 - Digital Input Disable Register 1
• Bit 2:0 – AMP0+D and ADC10:8 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
17.9 Amplifier
The AT90PWM81/161 features one differential amplified channel with programmable 5, 10, 20,
and 40 gain stage. Despite the result is given by the 10bit ADC, the amplifier has been sized to
give a 8bits resolution.
The negative input on the amplifier can be internally switched to the analog ground. However,
amplifier characteristics are specified with differential inputs.
Because the amplifier is a switching capacitor amplifier, it needs to be clocked by a synchroniza-
tion signal called in this document the amplifier synchronization clock. The amplifier samples the
input value at the falling edge of the synchronization signal. This allow to measure analog sig-
nals with same period as the synchronization. The maximum clock for the amplifier is 250kHz.
To ensure an accurate result in case of large voltage change, the amplifier input needs to have a
quite stable sampled input value during at least four Amplifier synchronization clock periods.
Bit 7 6543210
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 - - - - - - ADCL
Read/Write R R R R R R R R
R RRRRRRR
Initial Value 0 0 0 0 0 0 0 0
0 0000000
Bit 76543210
ADC8D
ACMP3D
ADC7D
AMP0-D
ADC5D
ACMP2D
ADC4D
ACMP3MD
ADC3D
ACMPMD
ADC2D
ACMP2MD
ADC1D ADC0D
ACMP1D
DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
- - - -
ACMP1MD AMP0+D
ADC10D ADC9D DIDR1
Read/Write - - R/W R/W R/W R/W R/W R/W
Initial Value00000000