Datasheet

221
7734Q–AVR–02/12
AT90PWM81/161
In case of trig on PSCnASY event, there is no flag. So, if ADSSEN is reset, a conversion will
start each time the trig event appears and the previous conversion is completed.
17.8.4 ADCH and ADCL - ADC Result Data Registers
When an ADC conversion is complete, the conversion results are stored in these two result data
registers.
When the ADCL register is read, the two ADC result data registers can’t be updated until the
ADCH register has also been read.
Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the
result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read
ADCH to have the conversion result.
17.8.4.1 ADLAR = 0
Table 17-6. ADC auto trigger source selection.
ADTS3 ADTS2 ADTS1 ADTS0 Description
0000Free running mode
0 0 0 1 Analog comparator 1
0 0 1 0 External Interrupt Request 0
0 0 1 1 Timer/Counter1 overflow
0 1 0 0 Timer/Counter1 capture event
0 1 0 1 PSCRASY event
0110PSC2ASY event
0 1 1 1 Analog comparator 2
1 0 0 0 Analog comparator 3
1001Reserved
1010Reserved
1011Reserved
1100Reserved
1101Reserved
1110Reserved
1111Reserved
Bit 7 6543210
- - - - - - ADC9 ADC8 ADCH
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
Read/Write R R R R R R R R
R RRRRRRR
Initial Value 0 0 0 0 0 0 0 0
0 0000000