Datasheet

7734Q–AVR–02/12

AT90PWM81/161

17.8.3 ADCSRB - ADC Control and Status Register B

• Bit 7 – ADHSM: ADC High Speed Mode

Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with

an ADC clock frequency higher than 200kHz.

• Bit 6 – ADNCDIS: ADC Noise Canceller Disable

Set this bit to disable automatic ADC start when entering Idle or ADC Noise reduction Modes.

Clear it to enable automatic ADC start when entering Idle or ADC reduction Modes.

The ADNCDIS must be set before entering Idle or ADC Noise reduction Modes if the ADC is run-

ning or Auto triggered to prevent false ADC restart.

• Bit 5 – Reserved

• Bit 4 – ADSSEN: ADC Single Shot Enable on PSC’s synchronization signals

Set this bit to enable single shot mode when auto trigger on PSCRASY & PSC2ASY. In this

case a single conversion will be performed and PSCRASY & PSC2ASY will be blocked until

ADCH reading.

Clear it to enable continuous conversion on PSCRASY & PSC2ASY auto triggering.

• Bit 3, 2, 1, 0– ADTS3:ADTS0: ADC Auto Trigger Source Selection Bits

These bits are only necessary in case the ADC works in auto trigger mode. It means if ADATE

bit in ADCSRA register is set.

In accordance with the Table 17-6 on page 221, these 3 bits select the interrupt event which will

generate the trigger of the start of conversion. The start of conversion will be generated by the

rising edge of the selected interrupt flag whether the interrupt is enabled or not.

Table 17-5. ADC prescaler selection.

ADPS2 ADPS1 ADPS0 Division factor

0002

0012

0104

0118

10016

10132

11064

111128

Bit 7 6543210

ADHSM ADNCDIS - ADSSEN ADTS3 ADTS2 ADTS1 ADTS0 ADCSRB

Read/Write R/W R/W - R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0