Datasheet

218
7734Q–AVR–02/12
AT90PWM81/161
• Bit 7, 6 – REFS1, 0: ADC V
REF
Selection Bits
These 2 bits determine the voltage reference for the ADC and for the other analog devices.
The different setting are shown in Table 17-3.
If these bits are changed during a conversion, the change will not take effect until this conversion
is complete (it means while the ADIF bit in ADCSRA register is set).
In case the internal V
REF
is selected, it is turned ON as soon as an analog feature needed it is
set.
• Bit 5 – ADLAR: ADC Left Adjust Result
Set this bit to left adjust the ADC result.
Clear it to right adjust the ADC result.
The ADLAR bit affects the configuration of the ADC result data registers. Changing this bit
affects the ADC data registers immediately regardless of any on going conversion. For a com-
plete description of this bit, see Section “ADCH and ADCL - ADC Result Data Registers”,
page 221.
• Bit 3, 2, 1, 0 – MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits
These 4 bits determine which analog inputs are connected to the ADC input. The different set-
ting are shown in Table 17-4.
Table 17-3. ADC voltage reference selection.
REFS1 REFS0 Description
Voltage reference PE3/AREF pin
0 0 External V
REF
External voltage reference
01AV
CC
1 0 Internal 2.56V reference voltage
External capacitor for decoupling of
the internal reference voltage
1 1 Internal 2.56V reference voltage PE3 pin free as port
Table 17-4. ADC input channel selection.
MUX3 MUX2 MUX1 MUX0 Description
0000ADC0
0001ADC1
0010ADC2
0011ADC3
0100ADC4
0101ADC5
0110ADC6
0111ADC7
1000ADC8
1001ADC9
1010ADC10
1011AMP0