Datasheet

217
7734Q–AVR–02/12
AT90PWM81/161
Example 1:
– ADMUX = 0xED (ADC3 - ADC2, 10× gain, 2.56V reference, left adjusted result)
– Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV
– ADCR = 512 × 10 × (300 - 500) / 2560 = -400 = 0x270
– ADCL will thus read 0x00, and ADCH will read 0x9C.
Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02
Example 2:
– ADMUX = 0xFB (ADC3 - ADC2, 1× gain, 2.56V reference, left adjusted result)
– Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV
– ADCR = 512 × 1 × (300 - 500) / 2560 = -41 = 0x029
– ADCL will thus read 0x40, and ADCH will read 0x0A.
Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29
17.8 ADC Register Description
The ADC of the AT90PWM81/161 is controlled through 3 different registers. The ADCSRA and
The ADCSRB registers which are the ADC Control and Status registers, and the ADMUX which
allows to select the V
REF
source and the channel to be converted.
The conversion result is stored on ADCH and ADCL register which contain respectively the most
significant bits and the less significant bits.
17.8.1 ADMUX - ADC Multiplexer Register
Table 17-2. Correlation between input voltage and output codes.
V
ADCn
Read code Corresponding decimal value
V
ADCm
+ V
REF
/GAIN 0x1FF 511
V
ADCm
+ 0.999 V
REF
/GAIN 0x1FF 511
V
ADCm
+ 0.998 V
REF
/GAIN 0x1FE 510
... ... ...
V
ADCm
+ 0.001 V
REF
/GAIN 0x001 1
V
ADCm
0x000 0
V
ADCm
- 0.001 V
REF
/GAIN 0x3FF -1
... ... ...
V
ADCm
- 0.999 V
REF
/GAIN 0x201 -511
V
ADCm
- V
REF
/GAIN 0x200 -512
Bit 7 6543210
REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 ADMUX
Read/Write R/W R/W R/W -R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0