Datasheet

212
7734Q–AVR–02/12
AT90PWM81/161
a. Keep analog signal paths as short as possible. Make sure analog tracks run over
the analog ground plane, and keep them well away from high-speed switching digi-
tal tracks.
b. The AV
CC
pin on the device should be connected to the digital V
CC
supply voltage
via an LC network as shown in Figure 17-9.
c. Use the ADC noise canceler function to reduce induced noise from the CPU.
d. If any ADC port pins are used as digital outputs, it is essential that these do not
switch while a conversion is in progress.
Figure 17-9. ADC power connections.
17.6.3 Offset Compensation Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-
surements as much as possible. The remaining offset in the analog path can be measured
directly by shortening both differential inputs using the AMPxIS bit with both inputs unconnected
(see “AMP0CSR - Amplifier 0 Control and Status register” on page 225). This offset residue can be
then subtracted in software from the measurement results. Using this kind of software based off-
set correction, offset on any channel can be reduced below one LSB.
17.6.4 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V
REF
in 2
n
steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2
n
-1.
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5LSB). Ideal value: 0LSB
100nF
Analog Ground Plane
VCC
AVCC
AGND
AREF
GND
10µH