Datasheet

208
7734Q–AVR–02/12
AT90PWM81/161
Figure 17-5. ADC timing diagram, single conversion.
Figure 17-6. ADC timing diagram, auto triggered conversion.
Figure 17-7. ADC timing diagram, free running conversion.
4
5 6 7 8 9 10 11
12 13 14 15 16
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
1
2 3
1 2 3 4 5 6 7 8 13 14 15 16
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
14 15 16
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample & Hold
MUX and REFS
Update