Datasheet

204
7734Q–AVR–02/12
AT90PWM81/161
Figure 17-1. Analog to digital converter block schematic.
MUX2 MUX1 MUX0REF S1 REF S0 A D L A R
ADPS2 ADPS1 ADPS0ADIEADEN ADSC ADATE ADIF
ADMUX
ADCSRA
ADTS2 ADTS1 ADTS0-
ADCSRB
Ed g e
Detect or
So u r c e s
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC10
AMP0+
-
+
AMP0CSR
+
-
SA R
10
10
ADCH
ADCL
Co ar se/ Fi n e DAC
10
Internal 2.56V
Re f e r e n c e
AVCC
PRESCALERCK
CK ADC
CONTROL
CK ADC
ADC CONVERSION
COM PLETE IRQ
GND
Band g ap
ADATE
ADTS3
Temp Sensor
VCC/4
ADC8
ADC9
AMP0GS
REFS0,REFS1
Logic
MUX3
Vref
AREF/ADC6
AMP0-/ADC7
ADSSENADNCDISADHSM
3