Datasheet

187
7734Q–AVR–02/12
AT90PWM81/161
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS
is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 14-3 on page 186 and Figure 14-4 on page 186 for an example. The
CPOL functionality is summarized below:
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to Figure 14-3 on page 186 and Figure 14-4 on page 186 for an
example. The CPOL functionality is summarized below:
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the clk
IO
frequency f
clkio
is shown in
Table 14-5:
Table 14-3. CPOL functionality.
CPOL Leading edge Trailing edge
0 Rising Falling
1 Falling Rising
Table 14-4. CPHA functionality.
CPHA Leading edge Trailing edge
0 Sample Setup
1 Setup Sample
Table 14-5. Relationship between SCK and the oscillator frequency.
SPI2X SPR1 SPR0 SCK frequency
000
f
clkio
/4
001
f
clkio
/16
010
f
clkio
/64
011
f
clkio
/128
100
f
clkio
/2
101f
clkio
/8
110
f
clkio
/32
111f
clkio
/64