Datasheet

7734Q–AVR–02/12

AT90PWM81/161

14. Serial Peripheral Interface – SPI:

14.1 Features

• Full-duplex, three-wire synchronous data transfer

• Master or Slave operation

• LSB first or MSB first data transfer

• Seven programmable bit rates

• End of transmission interrupt flag

• Write collision flag protection

• Wake-up from idle mode

• Double speed (CK/2) Master SPI mode

14.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

AT90PWM81/161 and peripheral devices or between several AVR devices.

The AT90PWM81/161 SPI includes the following features.

Figure 14-1. SPI block diagram

(1)

Note: 1. Refer to Figure 2-1 on page 3, and Table 9-3 on page 75 for SPI pin placement.

SPI2X

DIVIDER

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clk

MISO

MOSI

SCK