Datasheet

179
7734Q–AVR–02/12
AT90PWM81/161
• Bit 0 – PEOP0: End Of PSCR Interrupt
This bit is set by hardware when PSCR achieves its whole cycle.
Must be cleared by software by writing a one to its location.
Table 13-15. PSCR ramp number description.
PRN01 PRN00 Description
0 0 The last event which has generated an interrupt occurred during ramp 1
0 1 The last event which has generated an interrupt occurred during ramp 2
1 0 The last event which has generated an interrupt occurred during ramp 3
1 1 The last event which has generated an interrupt occurred during ramp 4