Datasheet

175
7734Q–AVR–02/12
AT90PWM81/161
• Bit 5- PBFM01: Balance Flank Width Modulation, bit 1
Defines the Flank Width Modulation, together with PBFM00 bit.
Note: 1. In one ramp mode, changing SA or SA+SB also affect On-Time; see Figure 13-6 on page 154.
• Bit 4 – PAOC0B: PSCR Asynchronous Output Control B
When this bit is set, Fault input selected to block B can act directly to PSCOUT01 output. See
Section “PSCR Input Configuration”, page 159.
• Bit 3 – PAOC0A: PSCR Asynchronous Output Control A
When this bit is set, Fault input selected to block A can act directly to PSCOUT00 output. See
Section “PSCR Input Configuration”, page 159.
• Bit 2- PBFM00: Balance Flank Width Modulation, bit 0
Defines the Flank Width Modulation, together with PBFM01 bit.
• Bit 1 – PCCYC0: PSCR Complete Cycle
When this bit is set, the PSCR completes the entire waveform cycle before halt operation
requested by clearing PRUN0. This bit is not relevant in slave mode (PARUN0 = 1).
• Bit 0 – PRUN0: PSCR Run
Writing this bit to one starts the PSCR.
When set, this bit prevails over PARUN0 bit.
13.23.8 PFRC0A - PSCR Input A Control Register
13.23.9 PFRC0B - PSCR Input B Control Register
The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The
2 blocks are identical, so they are configured on the same way.
Table 13-13. Flank Width mode selection.
PBFM01 PBFM00 Description
0 0 Flank Width Modulation operates on RB (On-Time 1 only)
01
Flank Width Modulation operates on RB + RA (On-Time 0 and On-
Time 1)
1 0 Flank Width Modulation operates on SB (Dead-Time 1 only)
(1)
11
Flank Width Modulation operates on SB +SA (Dead-Time 0 and
Dead-Time 1)
Bit 7 6543210
PCAE0A PISEL0A0 PELEV0A PFLTE0A PRFM0A3 PRFM0A2 PRFM0A1 PRFM0A0 PFRC0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 7 6543210
PCAE0B PISEL0B0 PELEV0B PFLTE0B PRFM0B3 PRFM0B2 PRFM0B1 PRFM0B0 PFRC0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000