Datasheet

172
7734Q–AVR–02/12
AT90PWM81/161
When this bit is set, I/O pin affected to PSCOUT01 is connected to the PSCR waveform genera-
tor B output and is set and clear according to the PSCR operation.
• Bit 1 – Reserved
• Bit 0 – POEN0A: PSCR OUT Part A Output Enable
When this bit is clear, I/O pin affected to PSCOUT00 acts as a standard port.
When this bit is set, I/O pin affected to PSCOUT00 is connected to the PSCR waveform genera-
tor A output and is set and clear according to the PSCR operation.
13.23.2 OCR0SAH and OCR0SAL - Output Compare SA Register
13.23.3 OCR0RAH and OCR0RAL - Output Compare RA Register
13.23.4 OCR0SBH and OCR0SBL - Output Compare SB Register
13.23.5 OCR0RBH and OCR0RBL - Output Compare RB Register
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously
compared with the PSCR counter value. A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the associated pin.
The Output Compare Registers RB contains also a 4-bit value that is used for the flank width
modulation.
The Output Compare Registers are 12-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers.
Bit 76543210
––––OCR0SA[11:8] OCR0SAH
OCR0SA[7:0] OCR0SAL
Read/Write WWWWWWWW
Initial Value00000000
Bit 76543210
––––OCR0RA[11:8] OCR0RAH
OCR0RA[7:0] OCR0RAL
Read/Write WWWWWWWW
Initial Value00000000
Bit 76543210
––––OCR0SB[11:8] OCR0SBH
OCR0SB[7:0] OCR0SBL
Read/Write WWWWWWWW
Initial Value00000000
Bit 76543210
OCR0RB[15:12] OCR0RB[11:8] OCR0RBH
OCR0RB[7:0] OCR0RBL
Read/Write WWWWWWWW
Initial Value00000000