Datasheet

171
7734Q–AVR–02/12
AT90PWM81/161
13.23 PSCR Register Definition
13.23.1 PSOC0 - PSCR Synchro and Output Configuration
• Bit 7– PISEL0A1: PSC Input Select for part A
Together with PISEL0A0, defines active signal on PSCR part A.
• Bit 6– PISEL0B1: PSCR Input Select for part B
Together with PISEL0B0, defines active signal on PSCR part B.
• Bit 5:4 – PSYNC01:0: Synchronization Out for ADC Selection)
Select the polarity and signal source for generating a signal which will be sent to the ADC for
synchronization.
• Bit 3 – Reserved
• Bit 2 – POEN0B: PSCR OUT Part B Output Enable
When this bit is clear, I/O pin affected to PSCOUT01 acts as a standard port.
Bit 7 6543210
PISEL0A1 PISEL0B1 PSYNC01 PSYNC00 - POEN0B - POEN0A PSOC0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 13-8. PSC trigger & fault input selection.
PISEL0A1 PISEL0A0 Description
0 0 PSCINr
0 1 Analog comparator output
1 0 PSCINrA
1 1 PSCINrB
Table 13-9. PSC trigger & fault input selection.
PISEL0B1 PISEL0B0 Description
0 0 PSCINr
0 1 Analog comparator output
1 0 PSCINrA
1 1 PSCINrB
Table 13-10. Synchronization source description in one/two/four Ramp modes.
PSYNC01 PSYNC00 Description
0 0 Send signal on leading edge of PSCOUT00 (match with OCR0SA)
01
Send signal on trailing edge of PSCOUT00 (match with OCR0RA or
fault/retrigger on part A)
1 0 Send signal on leading edge of PSCOUT01 (match with OCR0SB)
11
Send signal on trailing edge of PSCOUT01 (match with OCR0RB or
fault/retrigger on part B)