Datasheet

7734Q–AVR–02/12

AT90PWM81/161

Figure 13-32. Clock selection.

PCLKSELr bit in PSCR Configuration register (PCNFr) is used to select the clock source.

PPREr1/0 bits in PSCR Control Register (PCTLr) are used to select the divide factor of the

clock.

13.22 Interrupts

This section describes the specifics of the interrupt handling as performed in AT90PWM81/161.

13.22.1 List of Interrupt Vector

The PSCR provides 3 interrupt vectors:

• PSC0EC (End of Cycle): When enabled and when a match with OCRrRB occurs

• PSC0EEC (End of Enhanced Cycle): When enabled and when a match with OCRrRB

occurs at the 15th enhanced cycle

• PSC0CAPT (Capture Event): When enabled and one of the two following events occurs :

retrigger, capture of the PSCR counter or Synchro Error

See PSC0 Interrupt Mask Register page 177 and PSC0 Interrupt Flag Register page 178.

Table 13-7. Output clock versus selection and prescaler.

PCLKSELr PPREr1 PPREr0 CLKPSCr output

000CLK I/O

0 0 1 CLK I/O / 4

0 1 0 CLK I/O / 32

0 1 1 CLK I/O / 256

100CLK PLL

1 0 1 CLK PLL / 4

1 1 0 CLK PLL / 32

1 1 1 CLK PLL / 256

CLK

PSCr

CLK

PLL

I/O

CK/4

CK/32

CK/256

PRESCALER

PPREr1/0

PCLKSELr