Datasheet

163
7734Q–AVR–02/12
AT90PWM81/161
13.11 PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active
Figure 13-19. PSCr behavior versus PSCr Input A in Mode 3.
PSCR Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and
OT1.
When PSCR Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus
OT1 plus DT0 while PSCR Input A is in active state.
Even if PSCR Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-
pletely executed.
Figure 13-20. PSCr behavior versus PSCr Input B in Mode 3.
PSCR Input B is taken into account during DT1 and OT1 only. It has no effect during DT0 and
OT0.
When PSCR Input B event occurs, PSCR releases PSCOUTR1, jumps and executes DT0 plus
OT0 plus DT1 while PSCR Input B is in active state.
Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-
pletely executed.
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
DT0
OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1DT1 OT1 DT1 OT1
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
DT0
OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0